公开(公告)号：US20210391263A1

公开(公告)日：2021-12-16

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210280463A1

公开(公告)日：2021-09-09

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

公开(公告)号：US20200091053A1

公开(公告)日：2020-03-19

申请号：US16131511

申请日：2018-09-14

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Srinivas V. Pietambaram ,  Yonggang Li ,  Kristof Kuwawi Darmawikarta ,  Gang Duan ,  Krishna Bharath ,  Michael James Hill

IPC: H01L23/498 ,  H01F27/28 ,  H01F27/24 ,  H01F27/02 ,  H05K1/18

Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.

公开(公告)号：US20250125202A1

公开(公告)日：2025-04-17

申请号：US18984444

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H01L23/15 ,  H01L23/18 ,  H01L23/498 ,  H01L23/64

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening between the electronic component and a sidewall of the opening; and a through-glass via including a conductive material that extends through the glass layer.

公开(公告)号：US20250112085A1

公开(公告)日：2025-04-03

申请号：US18375244

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Ziyin Lin ,  Haobo Chen ,  Yiqun Bai ,  Kyle Arrington ,  Jose Waimin ,  Ryan Carrazzone ,  Hongxia Feng ,  Dingying Xu ,  Srinivas Pietambaram ,  Minglu Liu ,  Seyyed Yahya Mousavi ,  Xinyu Li ,  Gang Duan ,  Wei Li ,  Bin Mu ,  Mohit Gupta ,  Jeremy Ecton ,  Brandon C. Marin ,  Xiaoying Guo ,  Ashay Dani

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250105074A1

公开(公告)日：2025-03-27

申请号：US18977572

申请日：2024-12-11

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Wei Wei ,  Jose Fernando Waimin Almendares ,  Ryan Joseph Carrazzone ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Dingying Xu ,  Hongxia Feng ,  Yiqun Bai ,  Hiroki Tanaka ,  Brandon Christian Marin ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Gang Duan ,  Srinivas Venkata Ramanuja Pietambaram ,  Rui Zhang ,  Mohit Gupta

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.

公开(公告)号：US20250062206A1

公开(公告)日：2025-02-20

申请号：US18451150

申请日：2023-08-17

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Srinivas V. Pietambaram ,  Jeremy Ecton

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (IC) dies proximate to the second surface.

公开(公告)号：US20250006671A1

公开(公告)日：2025-01-02

申请号：US18217123

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Marcel Arlan Wall ,  Hamid Azimi ,  Rahul N. Manepalli ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Steve Cho ,  Thomas L. Sounart ,  Gang Duan ,  Jung Kyu Han ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01L23/00

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

公开(公告)号：US20250006609A1

公开(公告)日：2025-01-02

申请号：US18883752

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Ibrahim El Khatib ,  Jesse Cole Jones ,  Yi Li ,  Minglu Liu ,  Robin Shea McRee ,  Srinivas Venkata Ramanuja Pietambaram ,  Praveen Sreeramagiri

IPC: H01L23/498 ,  H01L23/15 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a second CTE different from the first CTE, the first through glass via electrically coupled to the second through glass via.

公开(公告)号：US20240347402A1

公开(公告)日：2024-10-17

申请号：US18756679

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Leonel Arana ,  Benjamin Duong

IPC: H01L23/13 ,  H01L23/15 ,  H01L25/065

CPC classification number: H01L23/13 ,  H01L23/15 ,  H01L25/0655

Abstract: Methods and apparatus to reduce delamination in hybrid cores are disclosed. An example hybrid core of an integrated circuit (IC) package comprises a frame, and a glass panel including a top surface, an edge adjacent the frame, and a tapered surface extending between the edge and the top surface.