Abstract:
Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.
Abstract:
A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for communication between an integrated circuit device and external structures. A process of forming the foamed bulk metallic glass electrical connection includes mixing bulk metallic glass with a blowing agent.
Abstract:
A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.
Abstract:
An integrated thin-film capacitor includes a dielectric disposed between a first electrode and a second electrode. The thin-film capacitor includes a dielectric disposed upon the first electrode, and the dielectric exhibits a substantially uniform heat-altered morphology along a line defined by a characteristic dimension thereof. A computing system is also disclosed that includes the thin-film capacitor.
Abstract:
A microelectronic device, a method of fabricating the device, and a system including the device. The device includes: a substrate including a polymer build-up layer, and a passive structure embedded in the substrate. The passive structure includes a top conductive layer overlying the polymer build-up layer, a dielectric layer overlying the top conductive layer, and a bottom conductive layer overlying the dielectric layer. The device further includes a conductive via extending through the polymer build-up layer and electrically insulated from the bottom conductive layer, an insulation material insulating the conductive via from the bottom conductive layer, and a bridging interconnect disposed at a side of the top conductive layer facing away from the dielectric layer, the bridging interconnect electrically connecting the conductive via to the top conductive layer.
Abstract:
An integrated thin-film capacitor includes a dielectric disposed between a first electrode and a second electrode. The thin-film capacitor includes a dielectric disposed upon the first electrode, and the dielectric exhibits a substantially uniform heat-altered morphology along a line defined by a characteristic dimension thereof. A computing system is also disclosed that includes the thin-film capacitor.
Abstract:
A process of forming a thin-film capacitor that includes sol-gel patterning of a dielectric thin film on a first electrode, lift-off removal of unwanted dielectric thin film, and mating the dielectric thin film with a second electrode. The thin-film capacitor exhibits a substantially uniform heat-altered morphology along a line defined by a characteristic dimension thereof. A computing system is also disclosed that includes the thin-film capacitor.
Abstract:
An embedded passive structure, its method of formation, and its intergration onto a substrate during fabrication are disclosed, In one embodiment the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower electrode layers are patterned in such a way as to reduce damage and improve cycle time. In one embodiment, the capacitor dielectric has a high dielectric constant and the substrate is an organic packaging substrate.
Abstract:
A thin-film capacitor assembly includes a first metal bottom electrode, a dielectric layer, a second metal etch-stop layer, and a subsequent metal top electrode. The first metal bottom electrode is in contact with the dielectric layer. The second metal etch-stop layer is in contact with the dielectric layer. The subsequent metal top electrode is in contact with the second metal etch-stop layer. Processing of the thin-film capacitor assembly includes totally removing a stiffener after assembling the first metal bottom electrode as a layer to the dielectric layer and the second metal etch-stop layer. The stiffener is removed from above and on the second metal etch-stop layer. The thin-film capacitor assembly is laminated to a mounting substrate.
Abstract:
Methods and structures related to film capacitors are disclosed. The capacitors include electrodes in a side-by-side or laterally offset configuration instead of a usual stacked configuration. The side-by-side configuration allows the interposing of the dielectric layer between the capacitor electrodes to be formed without as stringent a fabrication environment as is conventional. The electrodes are platinum in an embodiment. The dielectric is barium strontium titanate in an embodiment.