公开(公告)号：US07339244B2

公开(公告)日：2008-03-04

申请号：US11340135

申请日：2006-01-26

Applicant: Kanakasabapathi Subramanian ,  Noel C. MacDonald

Inventor： Kanakasabapathi Subramanian ,  Noel C. MacDonald

IPC: H01L27/14 ,  H01L29/82

CPC classification number: B81C1/00142 ,  B81B2203/0361 ,  B81C1/00071 ,  B81C1/00111 ,  B81C2201/0112 ,  Y10S977/70 ,  Y10S977/762

Abstract: A process cycles between etching and passivating chemistries to create rough sidewalls that are converted into small structures. In one embodiment, a mask is used to define lines in a single crystal silicon wafer. The process creates ripples on sidewalls of the lines corresponding to the cycles. The lines are oxidized in one embodiment to form a silicon wire corresponding to each ripple. The oxide is removed in a further embodiment to form structures ranging from micro sharp tips to photonic arrays of wires. Fluidic channels are formed by oxidizing adjacent rippled sidewalls. The same mask is also used to form other structures for MEMS devices.

Abstract translation: 蚀刻和钝化化学物质之间的过程循环，以产生转变成小结构的粗糙侧壁。 在一个实施例中，使用掩模来限定单晶硅晶片中的线。 该过程在对应于循环的线的侧壁上产生波纹。 在一个实施例中，线被氧化以形成对应于每个纹波的硅线。 在另一个实施方案中去除氧化物以形成从微尖端到光线阵列的结构。 通过氧化相邻的波纹侧壁形成流体通道。 同样的掩模也用于形成用于MEMS器件的其它结构。

公开(公告)号：US20060076312A1

公开(公告)日：2006-04-13

申请号：US11242916

申请日：2005-10-05

Applicant: Darrell McReynolds ,  Kia Silverbrook

Inventor： Darrell McReynolds ,  Kia Silverbrook

IPC: C23F1/00 ,  G01D15/00

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A process for facilitating modification of an etched trench is provided. The process comprises: (a) providing a wafer comprising an etched trench, the trench having a photoresist plug at its base; and (b) removing a portion of the photoresist by subjecting the wafer to a biased oxygen plasma etch. The process is particularly suitable for preparing a trench for subsequent argon ion milling. Printhead integrated circuits fabricated by a process according to the invention have improved ink channel surface profiles and/or surface properties.

公开(公告)号：US06818564B1

公开(公告)日：2004-11-16

申请号：US10324603

申请日：2002-12-20

Applicant: Colin Stephen Gormley

Inventor： Colin Stephen Gormley

IPC: H01L21302

CPC classification number: B81C1/00103 ,  B81B2203/0353 ,  B81C2201/0112 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086

Abstract: A semiconductor wafer comprises an SOI comprising a device layer on an oxide layer supported on a handle layer. Micro-mirrors are formed in the device layer, and access bores extend through the handle layer and the oxide layer to the micro-mirrors for accommodating optical fibers to the micro-mirrors. The access bores are accurately aligned with the micro-mirrors, and the access bores are accurately formed of circular cross-section. Each access bore comprises a tapered lead-in portion extending to a parallel portion. The diameter of the parallel portion is selected so that the optical fibers are a tight fit therein for securing the optical fibers in alignment with the micro-mirrors. The tapered lead-in portions of the access bores are formed to a first depth by a first dry isotropic etch for accurately forming the taper and the circular cross-section of the tapered lead-in portions. The parallel portions are formed from the first depth to a second face of the handle layer by a second dry etch, namely, an anisotropic etch carried out using the Bosch process. By so etching the access bores the access bores are accurately formed of circular transverse cross-section and of accurate dimensions.

Abstract translation: 半导体晶片包括SOI，其包括在手柄层上的氧化物层上的器件层。 微镜形成在器件层中，并且进入孔通过手柄层和氧化物层延伸到微反射镜，以将光纤容纳到微镜。 进入孔与微反射镜精确对准，并且进入孔精确地由圆形横截面形成。 每个通孔包括延伸到平行部分的锥形引入部分。 选择平行部分的直径，使得光纤紧密配合在其中以固定光学微镜与微反射镜对准。 进入孔的锥形引入部分通过第一干燥各向同性蚀刻形成第一深度，用于精确地形成锥形导入部分的锥形和圆形横截面。 平行部分通过第二干蚀刻即使用Bosch工艺进行的各向异性蚀刻从手柄层的第一深度到第二面形成。 通过这样蚀刻通路孔，准确地形成通孔，其圆形横截面和准确的尺寸。

公开(公告)号：US06767614B1

公开(公告)日：2004-07-27

申请号：US10021311

申请日：2001-12-19

Applicant: Wolfgang M. J. Hofmann ,  Hercules Neves ,  Noel C. MacDonald ,  Scott G. Adams

Inventor： Wolfgang M. J. Hofmann ,  Hercules Neves ,  Noel C. MacDonald ,  Scott G. Adams

IPC: B32B300

CPC classification number: B81C1/0015 ,  B81B2201/033 ,  B81B2203/0136 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0198 ,  Y10T428/13 ,  Y10T428/24273 ,  Y10T428/24562 ,  Y10T428/24744 ,  Y10T428/24802

Abstract: Improved fabrication processes for microelectromechanical structures, and unique structures fabricated by the improved processes are disclosed. In its simplest form, the fabrication process is a modification of the know SCREAM process, extended and used in such a way as to produce a combined vertical etch and release RIE process, which may be referred to as a “combination etch”. Fabrication of a single-level micromechanical structure using the process of the present invention includes a novel dry etching process to shape and release suspended single crystal silicon elements, the process combining vertical silicon reactive ion etching (Si-RIE) and release etches to eliminate the need to deposit and pattern silicon dioxide mask layers on the sides of suspended structures and to reduce the mechanical stresses in suspended structures caused by deposited silicon dioxide films.

Abstract translation: 公开了用于微机电结构的改进的制造工艺和通过改进的工艺制造的独特结构。 在其最简单的形式中，制造工艺是对已知SCREAM工艺的修改，扩展并以这样的方式使用，以便产生可被称为“组合蚀刻”的组合垂直蚀刻和释放RIE工艺。 使用本发明的方法制造单级微机械结构包括形成和释放悬浮的单晶硅元件的新型干蚀刻工艺，将垂直硅反应离子蚀刻（Si-RIE）和释放蚀刻相组合的工艺消除 需要在悬浮结构的两侧沉积并排列二氧化硅掩模层，并降低由沉积的二氧化硅膜引起的悬浮结构中的机械应力。

公开(公告)号：US20040124483A1

公开(公告)日：2004-07-01

申请号：US10334463

申请日：2002-12-31

Inventor： Aaron Partridge ,  Markus Lutz

IPC: H01L029/82 ,  H01L021/46

CPC classification number: B81C1/00063 ,  B81B3/0086 ,  B81C2201/0112 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: A method for adjusting with high precision the width of gaps between micromachined structures or devices in an epitaxial reactor environment. Providing a partially formed micromechanical device, comprising a substrate layer, a sacrificial layer including silicon dioxide deposited or grown on the substrate and etched to create desired holes and/or trenches through to the substrate layer, and a function layer deposited on the sacrificial layer and the exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Cleaning residues from the surface of the device, then epitaxially depositing a layer of gap narrowing material selectively on the surfaces of the device. The selection of deposition surfaces determined by choice of materials and the temperature and pressure of the epitaxy carrier gas. The gap narrowing epitaxial deposition continues until a desired gap width is achieved, as determined by, for example, an optical detection arrangement. Following the gap narrowing step, the micromachined structures or devices may be released from their respective underlying sacrificial layer.

Abstract translation: 一种用于在外延反应器环境中高精度调节微加工结构或器件之间的间隙宽度的方法。 提供部分形成的微机械装置，包括衬底层，牺牲层，包括沉积或生长在衬底上的二氧化硅，并被蚀刻以形成通过衬底层的期望的空穴和/或沟槽;以及沉积在牺牲层上的功能层， 衬底层的暴露部分，然后蚀刻以在其中限定微机械结构或器件。 蚀刻工艺暴露了去除的功能层材料下面的牺牲层。 从装置的表面清洁残留物，然后在装置的表面上选择性地外延沉积间隙变窄材料层。 通过选择材料和外延载气的温度和压力来确定沉积表面的选择。 缩小外延沉积的间隙持续到通过例如光学检测装置确定的期望的间隙宽度达到。 在间隙变窄步骤之后，微加工结构或器件可以从它们各自的底层牺牲层释放。

公开(公告)号：US5501893A

公开(公告)日：1996-03-26

申请号：US284490

申请日：1994-08-05

Applicant: Franz Laermer ,  Andrea Schilp

Inventor： Franz Laermer ,  Andrea Schilp

IPC: H01L21/302 ,  B81C1/00 ,  H01L21/3065 ,  H01L21/308 ,  C25F3/12 ,  B44C1/22

CPC classification number: H01L21/3085 ,  B81C1/00619 ,  H01L21/3065 ,  H01L21/30655 ,  B81C2201/0112 ,  Y10T428/24521

Abstract: A method of anisotropic plasma etching of silicon to provide laterally defined recess structures therein through an etching mask employing a plasma, the method including anisotropic plasma etching in an etching step a surface of the silicon by contact with a reactive etching gas to removed material from the surface of the silicon and provide exposed surfaces; polymerizing in a polymerizing step at least one polymer former contained in the plasma onto the surface of the silicon during which the surfaces that were exposed in a preceding etching step are covered by a polymer layer thereby forming a temporary etching stop; and alternatingly repeating the etching step and the polymerizing step. The method provides a high mask selectivity simultaneous with a very high anisotropy of the etched structures.

Abstract translation: PCT No.PCT / DE93 / 01129 Sec。 371日期：1994年8月5日 102（e）日期1994年8月5日PCT提交1993年11月27日PCT公布。 出版物WO94 / 14187 日期：1994年6月23日。一种通过使用等离子体的蚀刻掩模在其中提供横向限定的凹陷结构的硅的各向异性等离子体蚀刻的方法，所述方法包括在蚀刻步骤中的各向异性等离子体蚀刻，所述硅的表面通过与反应性 蚀刻气体以从硅表面去除材料并提供暴露的表面; 在聚合步骤中将包含在等离子体中的至少一种聚合物前体聚合到硅的表面上，在该表面处，在前面的蚀刻步骤中暴露的表面被聚合物层覆盖，从而形成临时蚀刻停止; 并交替重复蚀刻步骤和聚合步骤。 该方法与蚀刻结构的非常高的各向异性同时提供高掩模选择性。

公开(公告)号：US20240092634A1

公开(公告)日：2024-03-21

申请号：US17766770

申请日：2020-08-24

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Daiki SUZUKI ,  Takahiro MATSUMOTO ,  Tomoyuki IDE ,  Mikito TAKAHASHI

IPC: B81C1/00 ,  G02B26/08

CPC classification number: B81C1/00142 ,  B81C1/00952 ,  G02B26/0833 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133

Abstract: A method for manufacturing a mirror device, the method includes a first step of preparing a wafer having a support layer, a device layer, and an intermediate layer; a second step of forming a slit in the wafer such that the movable portion becomes movable with respect to the base portion by removing a part of each of the support layer, the device layer, and the intermediate layer from the wafer and forming a plurality of parts each corresponding to the structure in the wafer, after the first step; a third step of performing wet cleaning using a cleaning liquid after the second step; and a fourth step of cutting out each of the plurality of parts from the wafer after the third step. In the second step, a part of the intermediate layer is removed from the wafer by anisotropic etching.

公开(公告)号：US20170170059A1

公开(公告)日：2017-06-15

申请号：US15442085

申请日：2017-02-24

Applicant: MEMS Drive, Inc.

Inventor： Roman Gutierrez ,  Tony Tang ,  Xiaolei Liu ,  Guiqin Wang ,  Matthew NG

IPC: H01L21/768 ,  H01L23/485

CPC classification number: H01L21/76816 ,  B81B3/0045 ,  B81B7/0029 ,  B81B2203/0353 ,  B81C1/00674 ,  B81C1/00682 ,  B81C2201/0112 ,  B81C2201/0135 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/485 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/181

Abstract: A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structural characteristics desired in the MEMS device.

公开(公告)号：US09586207B2

公开(公告)日：2017-03-07

申请号：US14903960

申请日：2014-07-08

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sebastien Mermoz ,  Lea Di Cioccio ,  Thomas Magis ,  Loic Sanchez

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B01L3/00 ,  B81C1/00 ,  B81C3/00 ,  B81B1/00 ,  H01L23/13 ,  H01L21/3065

CPC classification number: B01L3/561 ,  B01L3/502 ,  B01L2200/12 ,  B01L2300/0838 ,  B81B1/002 ,  B81B2201/058 ,  B81C1/00555 ,  B81C1/00626 ,  B81C3/005 ,  B81C2201/0112 ,  H01L21/30655 ,  H01L23/13 ,  H01L2224/95146

Abstract: A method for capillary self-assembly of a plate and a carrier, including: forming an etching mask on a region of a substrate; reactive-ion etching the substrate, the etching using a series of cycles each including isotropic etching followed by surface passivation, wherein a duration of the isotropic etching for each cycle increases from one cycle to another, a ratio between durations of the passivation and etching of each cycle is lower than a ratio for carrying out a vertical anisotropic etching to form a carrier having an upper surface defined by the region and side walls defining an acute angle with the upper surface; removing the etching mask; placing a droplet on the upper surface of the carrier; and placing the plate on the droplet.

Abstract translation: 一种用于板和载体的毛细管自组装的方法，包括：在衬底的区域上形成蚀刻掩模; 反应离子蚀刻衬底，蚀刻使用一系列循环，每个循环包括各向同性蚀刻，然后进行表面钝化，其中每个循环的各向同性蚀刻的持续时间从一个循环增加到另一个周期，钝化和蚀刻的持续时间之间的比率 每个周期低于进行垂直各向异性蚀刻的比例，以形成具有由与上表面限定锐角的区域和侧壁限定的上表面的载体; 去除蚀刻掩模; 在载体的上表面上放置液滴; 并将板放在液滴上。

公开(公告)号：US09567207B2

公开(公告)日：2017-02-14

申请号：US14713287

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/84 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0041 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00293 ,  B81C2201/0112 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/0785

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first substrate having a frontside and a backside. The backside includes a first cavity extending into the first substrate. A dielectric layer is disposed on the backside of the first substrate, and includes an opening corresponding to the first cavity and a trench extending laterally away from the opening and terminating at a gas inlet recess. A recess in the frontside of the first substrate extends downwardly from the frontside to the dielectric layer. The recess has substantially vertical upper sidewalls which adjoin lower sidewalls which taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which circumscribe the gas inlet recess. A conformal sealant layer is arranged over the frontside of the first substrate, along the substantially vertical upper sidewalls, and along the lower sidewalls. The sealant layer hermetically seals the gas inlet recess.

Abstract translation: 提供集成电路（IC）装置。 IC器件包括具有前侧和后侧的第一基板。 背面包括延伸到第一基底中的第一腔。 电介质层设置在第一基板的背面，并且包括对应于第一空腔的开口和从开口横向延伸并终止于气体入口凹部的沟槽。 第一衬底的前侧的凹部从前侧向下延伸到电介质层。 凹部具有基本上垂直的上侧壁，其邻接下部侧壁，所述下侧壁从基本上垂直的侧壁向内逐渐向包围气体入口凹部的电介质层上的点倾斜。 共形密封剂层沿着基本垂直的上侧壁以及沿着下侧壁设置在第一基板的前侧上。 密封剂层密封气体入口凹部。