公开(公告)号：US09768013B2

公开(公告)日：2017-09-19

申请号：US15247586

申请日：2016-08-25

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Schubert S. Chu ,  Jessica S. Kachian ,  David Thompson ,  Jeffrey Anthis

IPC: H01L21/02 ,  H01L21/283 ,  H01J37/32 ,  C23C16/455 ,  C23C16/04

CPC classification number: H01L21/0228 ,  C23C16/04 ,  C23C16/45544 ,  H01J37/32009 ,  H01J37/32357 ,  H01J37/32522 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02049 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/67745

Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.

公开(公告)号：US09752226B2

公开(公告)日：2017-09-05

申请号：US15389259

申请日：2016-12-22

Applicant: CANON ANELVA CORPORATION

Inventor： Koji Tsunekawa

IPC: C23C14/35 ,  C23C14/14 ,  C23C14/56 ,  C23C14/50 ,  C23C14/34 ,  C23C14/08 ,  C23C14/06 ,  H01F41/18 ,  H01J37/34 ,  H01J37/32

CPC classification number: C23C14/14 ,  C23C14/067 ,  C23C14/081 ,  C23C14/34 ,  C23C14/3407 ,  C23C14/345 ,  C23C14/3464 ,  C23C14/505 ,  C23C14/568 ,  C23C14/5806 ,  C23C14/5853 ,  C23C28/321 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  H01F41/18 ,  H01J37/32899 ,  H01J37/3405 ,  H01J37/3411 ,  H01J37/3417 ,  H01L21/67207 ,  H01L43/08 ,  H01L43/12

Abstract: The present invention provides a manufacturing apparatus which can realize so-called sequential substrate transfer and can improve throughput, even when one multi-layered thin film includes plural layers of the same film type. A manufacturing apparatus according to an embodiment of the present invention includes a transfer chamber, three sputtering deposition chambers each including one sputtering cathode, two sputtering deposition chambers each including two or more sputtering cathodes, and a process chamber for performing a process other than sputtering, and the three sputtering deposition chambers, the two sputtering deposition chambers, and the process chamber are arranged around the transfer chamber so that each is able to perform delivery and receipt of the substrate with the transfer chamber.

公开(公告)号：US20170221681A1

公开(公告)日：2017-08-03

申请号：US15328860

申请日：2015-07-13

Applicant: TOKYO ELECTRON LIMITED

Inventor： Satoru KAWAKAMI

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/3244 ,  F16B5/10 ,  H01J37/3211 ,  H01J37/32743 ,  H01J37/32788 ,  H01J37/32807 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/67069 ,  H01L21/67167 ,  H01L21/67178 ,  H01L21/6719 ,  H01L21/67248

Abstract: A substrate processing system is provided with a transfer module that transports a substrate to be processed, and a plurality of processing units which are mounted and arranged vertically along a side surface of the transfer module, and each of which processes the substrate to be processed. Each of the processing units includes a chamber, a shower head, and a stage. The chamber includes an upper unit that includes a part of a sidewall forming a space in the chamber and that is fitted with the shower head, and a lower unit including the remaining portion of the side wall in the chamber and fitted with the stage. The upper unit and the lower unit are separable in a direction different from the direction in which the plurality of processing units are arranged.

公开(公告)号：US09721839B2

公开(公告)日：2017-08-01

申请号：US14738389

申请日：2015-06-12

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Mohammad Kamruzzaman Chowdhury ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/02 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/82 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02057 ,  H01L21/02076 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/67207 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.

公开(公告)号：US20170178920A1

公开(公告)日：2017-06-22

申请号：US15449799

申请日：2017-03-03

Applicant: Lam Research Corporation

Inventor： Nikhil Dole ,  Eric A. Hudson ,  George Matamis

IPC: H01L21/3065 ,  C23C16/52 ,  C23C16/455 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/30655 ,  H01J37/32091 ,  H01J37/32137 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/3321 ,  H01J2237/334 ,  H01J2237/3347 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/67069 ,  H01L28/00

Abstract: Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective film on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective film may be deposited under different conditions (e.g., pressure, duration of reactant delivery, duration of plasma exposure, RF power, and/or RF duty cycle, etc.) in different deposition operations. Such conditions may affect the degree of conformality at which the protective film forms. In various embodiments, one or more protective films may be sub-conformal. In these or other embodiments, one or more other protective films may be conformal.

公开(公告)号：US09676010B2

公开(公告)日：2017-06-13

申请号：US14904743

申请日：2014-07-15

Applicant: Universidade Federal De Santa Catarina (UFSC) ,  Whirlpool S.A.

Inventor： Roberto Binder ,  Aloisio Nelmo Klein ,  Cristiano Binder ,  Gisele Hammes

IPC: C23F1/00 ,  B08B7/00 ,  H01J37/32 ,  H01L21/67 ,  B22F3/00 ,  B22F3/24

CPC classification number: B08B7/0035 ,  B22F3/003 ,  B22F3/24 ,  B22F2003/241 ,  B22F2003/248 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32834 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/335 ,  H01L21/67109 ,  H01L21/67173 ,  H01L21/6719

Abstract: The plasma reactor comprises a reaction chamber (23) connectable to a source of ionizable gases (25) and to a heating device (80), said reactor (10) being subjected to the phases of heating (A), cleaning (L) and/or surface treatment (S), cooling (R), unloading (D) and loading (C) of metallic pieces (1). The installation comprises: at least two reactors (10), each being selectively and alternately connected to: the same source of ionizable gases (25); the same vacuum source (60); the same electrical energy source (50); and to the same heating device (80), the latter being displaceable between operative positions, in each of which surrounding laterally and superiorly a respective reactor (10), while the latter is in its heating phase (A) and cleaning phase (L) and/or in the surface treatment phase (S) of the metallic pieces (1).

公开(公告)号：US20170133228A1

公开(公告)日：2017-05-11

申请号：US15404561

申请日：2017-01-12

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L21/67

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US20170133202A1

公开(公告)日：2017-05-11

申请号：US14936437

申请日：2015-11-09

Applicant: Lam Research Corporation

Inventor： Ivan L. Berry, III

IPC: H01J37/32 ,  C23C16/455 ,  H01L21/3065 ,  C23C16/511 ,  H01L21/67 ,  H01L21/02

CPC classification number: H01J37/3222 ,  C23C16/45544 ,  C23C16/45565 ,  C23C16/511 ,  H01J37/321 ,  H01J37/32238 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32899 ,  H01J37/32926 ,  H01L21/0228 ,  H01L21/67069

Abstract: Disclosed herein are methods of modifying a reaction rate on a semiconductor substrate in a processing chamber which utilize a phased-array of microwave antennas. The methods may include energizing a plasma in a processing chamber, emitting a beam of microwave radiation from a phased-array of microwave antennas, and directing the beam into the plasma so as to cause a change in a reaction rate on the surface of a semiconductor substrate inside the processing chamber. Also disclosed herein are particular embodiments of phased-arrays of microwave antennas, as well as semiconductor processing apparatuses which include a phased-array of microwave antennas configured to emit a beam of microwave radiation into a processing chamber.

公开(公告)号：US20170053819A1

公开(公告)日：2017-02-23

申请号：US14846635

申请日：2015-09-04

Applicant: Lam Research Corporation

Inventor： Brett C. Richardson

IPC: H01L21/67 ,  C23C16/50 ,  H01L21/677 ,  C23C16/52 ,  G01B11/14 ,  G01B7/14 ,  H01J37/32 ,  C23C16/455

CPC classification number: H01L21/67288 ,  G01N21/88 ,  G01N21/9501 ,  H01J37/3178 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32733 ,  H01J37/32743 ,  H01J37/32899 ,  H01J37/32908 ,  H01J2237/332 ,  H01J2237/334 ,  H01L21/67253 ,  H01L21/67259 ,  H01L21/67742 ,  H01L21/67748

Abstract: Methods, systems, and computer programs are presented for determining wear of a consumable part in a semiconductor processing apparatus. One chamber includes a reference part, a consumable part, a transfer arm for transferring the substrate into the chamber, a sensor on the transfer arm, and a controller. The reference part is not subject to wear during operation of the chamber, while the consumable part is subject to wear. The sensor is configured to measure a first distance from the sensor to a surface of the consumable part as the transfer arm travels near the consumable part, and the sensor is configured to measure a second distance from the sensor to a surface of the reference part as the transfer arm travels near the reference part. The controller determines the wear amount of the consumable part based on the first distance and the second distance.

Abstract translation: 呈现了用于确定半导体处理装置中的消耗部件的磨损的方法，系统和计算机程序。 一个腔室包括参考部件，消耗部件，用于将衬底转移到腔室中的传送臂，传送臂上的传感器和控制器。 参考部件在室的运行期间不会磨损，而消耗部件磨损。 传感器被配置成当传送臂行进在消耗部分附近时测量从传感器到消耗部件的表面的第一距离，并且传感器被配置成测量从传感器到参考部分的表面的第二距离，如 传送臂在参考部分附近行进。 控制器基于第一距离和第二距离来确定消耗部件的磨损量。

公开(公告)号：US09576775B2

公开(公告)日：2017-02-21

申请号：US14532894

申请日：2014-11-04

Applicant: relyon plasma GmbH ,  EPCOS AG

Inventor： Stefan Nettesheim ,  Georg Kuegerl ,  Markus Puff

IPC: B01J19/08 ,  H01J37/32 ,  H05H1/36 ,  H05H1/44

CPC classification number: H01J37/32449 ,  H01J37/32899 ,  H05H1/36 ,  H05H1/44

Abstract: The invention relates to a plasma generation device comprising a plurality of plasma modules for generating a plasma. Each plasma module has a module housing with at least one gas inlet for supplying a process gas. Furthermore, a discharge device for generating the plasma from the process gas and a plasma outlet are provided. The plasma generation device has at least two plasma modules for generating a plasma. Each plasma module has at least one gas outlet for some of the process gas, wherein the at least one gas outlet of at least one plasma module issues into a respective gas inlet of another plasma module.

Abstract translation: 本发明涉及一种等离子体产生装置，其包括用于产生等离子体的多个等离子体模块。 每个等离子体模块具有模块壳体，其具有至少一个气体入口用于提供处理气体。 此外，提供了用于从处理气体产生等离子体的排出装置和等离子体出口。 等离子体产生装置具有用于产生等离子体的至少两个等离子体模块。 每个等离子体模块具有用于一些工艺气体的至少一个气体出口，其中至少一个等离子体模块的至少一个气体出口发射到另一个等离子体模块的相应气体入口。