公开(公告)号：US20090315062A1

公开(公告)日：2009-12-24

申请号：US12145395

申请日：2008-06-24

Applicant: Wen-Herng Su ,  Junying Lu ,  Ho-Shang Lee

Inventor： Wen-Herng Su ,  Junying Lu ,  Ho-Shang Lee

IPC: H01L33/00

CPC classification number: H01L33/483 ,  H01L33/005 ,  H01L33/60 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K1/053 ,  H05K1/162 ,  H05K1/183 ,  H05K2201/0116 ,  H05K2201/0179 ,  H05K2201/10106 ,  H05K2203/0315 ,  Y10S362/80 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/53113 ,  H01L2924/00014 ,  H01L2924/00

Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.

Abstract translation: 本发明涉及发光二极管或LED电路的热管理，光提取和成本效益。 描述了集成电路LED基座，用于大功率LED的封装。 LED基座提供高导热性，同时保持电气绝缘。 特别地，描述了用于阳极氧化高导热性铝合金板以形成多孔氧化铝层和无孔氧化铝层的工艺。 该阳极氧化铝合金板作为优异的电绝缘体，并且还提供用于制造高密度和大功率多电平电路的表面形态和机械性能。

公开(公告)号：US20090290314A1

公开(公告)日：2009-11-26

申请号：US12533448

申请日：2009-07-31

Applicant: John M. Bedinger ,  Michael A. Moore

Inventor： John M. Bedinger ,  Michael A. Moore

IPC: H05K1/18

CPC classification number: H05K3/284 ,  H01L23/3192 ,  H01L23/4821 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/8592 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/1322 ,  Y10T29/49124 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49982 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A circuit board assembly includes a circuit board having an outer surface, the outer surface being configured with a plurality of discrete electrical components that are each manufactured independently of one another. The circuit board assembly further includes a domed lid enclosure disposed over one of the plurality of discrete electrical components and an additional dielectric coating overlying the outer surface and the domed lid enclosure.

Abstract translation: 电路板组件包括具有外表面的电路板，所述外表面配置有彼此独立制造的多个分立电气部件。 电路板组件还包括设置在多个离散电气部件中的一个上的圆顶形盖子外壳和覆盖外表面和圆顶形盖子外壳的附加电介质涂层。

公开(公告)号：US20090288876A1

公开(公告)日：2009-11-26

申请号：US12533409

申请日：2009-07-31

Applicant: John M. Bedinger ,  Michael A. Moore

Inventor： John M. Bedinger ,  Michael A. Moore

IPC: H05K5/02 ,  H05K1/02

CPC classification number: H05K3/284 ,  H01L23/3192 ,  H01L23/4821 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/8592 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/1322 ,  Y10T29/49124 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49982 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A circuit board assembly includes a circuit board having an outer surface that is configured with a plurality of discrete electrical components that are each manufactured independently of one another. The circuit board assembly further includes a first protective dielectric layer overlying the outer surface, and a second dielectric layer overlying the first protective dielectric layer and the discrete electrical components. The second dielectric layer includes a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 3.0, a dielectric loss less than 0.008, a moisture absorption less than 0.04 percent, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 300° Celsius, pinhole free in films greater than 50 Angstroms, hydrophobic with a wetting angle greater than 45 degrees, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 30%.

Abstract translation: 电路板组件包括具有外表面的电路板，该外表面被配置有彼此独立制造的多个分立电气部件。 电路板组件还包括覆盖在外表面上的第一保护电介质层和覆盖第一保护介电层和分立电组件的第二电介质层。 第二电介质层包括弹性模量小于3.5千兆帕（GPa），介电常数小于3.0的介电材料，小于0.008的介电损耗，小于0.04％的吸湿性，超过的击穿电压强度 200万伏/厘米（MV /厘米），温度稳定至300摄氏度，大于50埃的薄膜中无针孔，疏水性大于45度的润湿角度，能够在3D结构下保形地沉积， 厚度均匀度小于或等于30％。

公开(公告)号：US20090263641A1

公开(公告)日：2009-10-22

申请号：US12104152

申请日：2008-04-16

Applicant: Sidney Edward Martin, III ,  Eric Roger Dawicki ,  Angela Michele Dawicki

Inventor： Sidney Edward Martin, III ,  Eric Roger Dawicki ,  Angela Michele Dawicki

IPC: B32B27/06 ,  C23C16/02 ,  B32B9/04 ,  B32B15/04 ,  B32B27/00

CPC classification number: B05D1/60 ,  H05K3/284 ,  H05K2201/0179 ,  Y10T428/249921 ,  Y10T428/31504 ,  Y10T428/31544 ,  Y10T428/31678 ,  Y10T428/31721

Abstract: The present invention provides a novel method to apply Silquest to an object as a vapor, a related method to coat objects with Parylene and Silquest, and objects coated by these methods. The invention further provides an vapor deposition apparatus with multi-temperature zone furnaces that is useful for applying a Parylene coating to objects. The invention further provides objects coated with Silquest and polymers, including Parylene, where the objects are incompatible with immersion in water.

Abstract translation: 本发明提供了一种将Silquest作为蒸气施用于物体的新方法，用Parylene和Silquest涂覆物体的相关方法以及通过这些方法涂覆的物体。 本发明还提供了一种具有多温区域熔炉的气相沉积设备，其可用于将Parylene涂层施加到物体上。 本发明还提供涂覆有Silquest和聚合物（包括Parylene）的物体，其中物体与浸入水中不相容。

公开(公告)号：US07601181B2

公开(公告)日：2009-10-13

申请号：US11923974

申请日：2007-10-25

Applicant: William Borland ,  Ian Burn ,  Jon Fredrick Ihlefeld ,  Jon Paul Maria ,  Seigi Suh

Inventor： William Borland ,  Ian Burn ,  Jon Fredrick Ihlefeld ,  Jon Paul Maria ,  Seigi Suh

IPC: H01L21/8242 ,  H01G9/00

CPC classification number: H01L21/02197 ,  C01G23/006 ,  C01P2004/82 ,  C01P2006/40 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02337 ,  H01L21/31691 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T428/31678

Abstract: Described herein are methods for making articles comprising a dielectric layer formed from any solution composition that can form barium titanate during firing and containing manganese in an amount between 0.002 and 0.05 atom percent of the solution composition, wherein the dielectric layer has been formed on metal foil and fired in a reducing atmosphere.

Abstract translation: 本文描述了制备制品的方法，所述方法包括由任意溶液组合物形成的介电层，所述溶液组合物在焙烧期间可以形成钛酸钡并且含有0.002至0.05原子％的溶液组成的量，其中介电层已经形成在金属箔 并在还原气氛中开火。

公开(公告)号：US07561406B2

公开(公告)日：2009-07-14

申请号：US11730154

申请日：2007-03-29

Applicant: Hitoshi Saita ,  Yuko Saya ,  Kiyoshi Uchida ,  Kenji Horino

Inventor： Hitoshi Saita ,  Yuko Saya ,  Kiyoshi Uchida ,  Kenji Horino

IPC: H01G4/008 ,  H01G4/06 ,  H01G7/00

CPC classification number: H01G4/008 ,  H01G4/33 ,  H01L27/016 ,  H01L27/0682 ,  H01L27/0802 ,  H01L27/0811 ,  H01L28/55 ,  H05K1/09 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T29/417 ,  Y10T29/435

Abstract: A thin film capacitor with high capacity and low leak current is provided. The thin film capacitor includes a nickel substrate with nickel (Ni) purity of 99.99 weight percent or above, and a dielectric layer and an electrode layer disposed in this order on the nickel substrate. The thin film capacitor is typically manufactured as follows. A precursor dielectric layer is formed on a nickel substrate with nickel purity of 99.99 weight percent or above, and is subjected to annealing to form a dielectric layer. The diffusion of impurities from the nickel substrate to the precursor dielectric layer during annealing is suppressed.

Abstract translation: 提供了具有高容量和低漏电流的薄膜电容器。 薄膜电容器包括镍（Ni）纯度为99.99重量％以上的镍基板，以及依次设置在镍基板上的电介质层和电极层。 薄膜电容器通常如下制造。 在镍基底上形成前体电介质层，其镍纯度为99.99重量％以上，并进行退火以形成电介质层。 抑制了退火时的杂质从镍基体向前体电介质层的扩散。

公开(公告)号：US20090141438A1

公开(公告)日：2009-06-04

申请号：US12063152

申请日：2006-10-30

Applicant: Tetsuya Aita ,  Yoshimasa Chikama

Inventor： Tetsuya Aita ,  Yoshimasa Chikama

IPC: H05K1/00 ,  G06F1/16

CPC classification number: H05K3/323 ,  G02F1/13452 ,  H01L24/16 ,  H01L24/83 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H05K3/3452 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0989 ,  H05K2201/10674 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/05599

Abstract: An electrode connection structure including a first circuit component including a resin plate, a barrier film stacked on a surface of the resin plate, a circuit section formed on the barrier film and a first electrode provided on the surface of the resin plate on which the barrier film is stacked, and a second circuit component arranged to face the first circuit component and having a second electrode facing the first electrode, wherein the first and second electrodes are electrically connected via pressure applied thereto in the directions approaching each other and a portion of the barrier film surrounding the first electrode is at least partially removed from the surface of the resin plate.

Abstract translation: 一种电极连接结构，包括：第一电路部件，包括树脂板，层叠在树脂板的表面上的阻挡膜，形成在阻挡膜上的电路部分和设置在树脂板的表面上的第一电极， 并且第二电路部件布置成面向第一电路部件并且具有面向第一电极的第二电极，其中第一和第二电极经由施加到其上的压力在彼此接近的方向上电连接，并且部分 围绕第一电极的阻挡膜至少部分地从树脂板的表面去除。

公开(公告)号：US20090139760A1

公开(公告)日：2009-06-04

申请号：US12216747

申请日：2008-07-10

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H01R12/04 ,  H05K3/00

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including an insulation layer and a first interlayer resin insulation layer provided on the insulation layer. A layered capacitor section is provided on the first interlayer resin insulation layer and has a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. Also included is a second interlayer resin insulation layer provided on the first interlayer resin insulation layer and the layered capacitor section, and a metal thin-film layer provided over the layered capacitor section and on the second interlayer resin insulation layer. An outermost interlayer resin insulation layer is provided on the second interlayer resin insulation layer and the metal thin-film layer, and a mounting section is provided on the outermost interlayer resin insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each interlayer resin insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals, and second via conductors that electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在所述绝缘层上的绝缘层和第一层间树脂绝缘层。 层叠电容器部分设置在第一层间树脂绝缘层上，并且具有高电介质层和夹在高电介质层中的第一和第二层状电极。 还包括设置在第一层间树脂绝缘层和层状电容器部分上的第二层间树脂绝缘层和设置在层状电容器部分和第二层间树脂绝缘层上的金属薄膜层。 在第二层间树脂绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层，并且在最外层的层间树脂绝缘层上设置安装部，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个层间树脂绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体和将第二层状电极电连接到第二外部端子的第二通路导体。

公开(公告)号：US07536780B2

公开(公告)日：2009-05-26

申请号：US11311568

申请日：2005-12-19

Applicant: Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Kiyoshi Oi ,  Akio Rokugawa

Inventor： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Kiyoshi Oi ,  Akio Rokugawa

IPC: H05K3/36

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/025 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: The present invention discloses a method of manufacturing a wiring substrate to which a semiconductor chip mounted. The method includes the steps of forming a base, forming a peeling layer on the base, forming a capacitor having a plurality of layers on the peeling layer, and forming a wiring part in the capacitor for connecting the capacitor to the semiconductor chip.

Abstract translation: 本发明公开了一种制造安装有半导体芯片的布线基板的方法。 该方法包括以下步骤：形成基底，在基底上形成剥离层，在剥离层上形成具有多个层的电容器，以及在用于将电容器连接到半导体芯片的电容器中形成布线部分。

公开(公告)号：US07514038B2

公开(公告)日：2009-04-07

申请号：US10861976

申请日：2004-06-04

Applicant: Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

Inventor： Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

IPC: G01N21/00 ,  H05K3/40 ,  H05K1/03

CPC classification number: H05K3/28 ,  A61B5/0006 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1147 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/308

Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.

Abstract translation: 具有从衬底的一侧延伸到另一侧的气密密封通孔的衬底及其制造方法。 通孔可以填充有导电材料，例如无油墨。 由导电材料形成的导电路径有助于将基板的一侧与另一侧密封。 衬底的一侧可以包括感测元件，并且衬底的另一侧可以包括感测电子器件。