公开(公告)号：US08427839B2

公开(公告)日：2013-04-23

申请号：US12678511

申请日：2008-09-09

Applicant: Dieter Eissler

Inventor： Dieter Eissler

IPC: H05K7/10

CPC classification number: H01L25/167 ,  H01L24/73 ,  H01L25/0756 ,  H01L33/62 ,  H01L33/641 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12041 ,  H05K3/303 ,  H05K2201/09045 ,  H05K2201/10106 ,  H05K2203/167 ,  H05K2203/168 ,  Y02P70/613 ,  H01L2924/00

Abstract: An arrangement includes an optoelectronic component with two contacts; at least one further component part; at least one contact arranged between the optoelectronic component and the further component part; and at least one web arranged between the optoelectronic component and the further component part.

Abstract translation: 一种布置包括具有两个触点的光电子部件; 至少一个另外的部件; 布置在所述光电子部件和所述另外的部件之间的至少一个接触件; 以及布置在所述光电子部件和所述另外的部件之间的至少一个网。

公开(公告)号：US20120327608A1

公开(公告)日：2012-12-27

申请号：US13441598

申请日：2012-04-06

Applicant: John A. ROGERS ,  Matthew Meitl ,  Yugang Sun ,  Heung Cho Ko ,  Andrew Carlson ,  Won Mook Choi ,  Mark Stoykovich ,  Hanging Jiang ,  Yonggang Huang ,  Ralph G. Nuzzo ,  Zhengtao Zhu ,  Etienne Menard ,  Dahl-Young Khang

Inventor： John A. ROGERS ,  Matthew Meitl ,  Yugang Sun ,  Heung Cho Ko ,  Andrew Carlson ,  Won Mook Choi ,  Mark Stoykovich ,  Hanging Jiang ,  Yonggang Huang ,  Ralph G. Nuzzo ,  Zhengtao Zhu ,  Etienne Menard ,  Dahl-Young Khang

IPC: H05K7/06

CPC classification number: H01L29/72 ,  H01L21/02422 ,  H01L21/02628 ,  H01L21/4846 ,  H01L21/8258 ,  H01L23/5387 ,  H01L27/12 ,  H01L29/0657 ,  H01L2924/12041 ,  H01L2924/13091 ,  H05K1/0283 ,  H05K3/20 ,  H05K3/22 ,  H05K2201/0133 ,  H05K2201/09045 ,  H05K2203/0271 ,  H01L2924/00

Abstract: In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract translation: 一方面，本发明提供了拉伸，压缩，弯曲或其它变形时能够提供良好性能的可拉伸和可选择的可印刷的部件，例如半导体和电子电路，以及制造或调谐这种可拉伸部件的相关方法。 对于一些应用而言，优选的可拉伸半导体和电子电路除了是可拉伸的之外是柔性的，因此能够沿着一个或多个轴显着地伸长，弯曲，弯曲或其它变形。 此外，本发明的可拉伸半导体和电子电路适用于宽范围的器件配置，以提供完全灵活的电子和光电器件。

公开(公告)号：US20120234582A1

公开(公告)日：2012-09-20

申请号：US13484719

申请日：2012-05-31

Applicant: Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

Inventor： Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H05K1/03 ,  H05K3/00

CPC classification number: H05K1/0224 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract translation: 提供传输线的磁场分布和互电容控制。 通过将参考平面层附着到介电材料层并且将第一迹线附接到电介质材料的第二表面来制造第一电路板。 修改参考平面层的表面轮廓以减小通过参考平面层的返回电流信号路径的电阻，以减小第一迹线和第二迹线之间的磁场耦合。 通过将参考平面层附着到电介质材料层，将迹线附着到电介质材料上，以及在迹线上的介电材料层上形成焊料掩模层来制造第二电路板。 修改焊接掩模层的有效介电常数以减小或增加介电材料上的第一迹线和第二迹线之间的互电容。

公开(公告)号：US20120060368A1

公开(公告)日：2012-03-15

申请号：US13301812

申请日：2011-11-22

Applicant: Cheng-Po Yu ,  Han-Pei Huang

Inventor： Cheng-Po Yu ,  Han-Pei Huang

IPC: H05K3/22

CPC classification number: H05K1/11 ,  H05K1/0284 ,  H05K1/142 ,  H05K3/185 ,  H05K3/4007 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09163 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1327 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T428/24802 ,  Y10T428/24917

Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.

Abstract translation: 一种制造电路板结构的方法，包括提供电路板主体，通过封装所述电路板主体的至少一部分来形成具有非板型，立体结构和至少一个刮痕表面的模制的不规则塑料体 并且在所述模制的不规则塑料体上形成第一三维电路图案，从而限定三维电路装置。

公开(公告)号：US08017450B2

公开(公告)日：2011-09-13

申请号：US12364517

申请日：2009-02-03

Applicant: Nadine Lee-Yen Chew ,  Elmer Dimaculangan Perez ,  Kiangkai Tankongchumruskul

Inventor： Nadine Lee-Yen Chew ,  Elmer Dimaculangan Perez ,  Kiangkai Tankongchumruskul

IPC: H01L23/24 ,  H01L27/15

CPC classification number: H01L21/56 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/85947 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/20753 ,  H05K1/189 ,  H05K2201/09045 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/20754 ,  H01L2224/05599

Abstract: A method of forming an asymmetrical encapsulant bead on a series of wire bonds electrically connecting a micro-electronic device to a series of conductors, the micro-electronic device having a planar active surface. The method has the steps of positioning the die and the wire bonds beneath an encapsulant jetter that jets drops of encapsulant on to the wire bonds, the drops of encapsulant following a vertical trajectory, tilting the die such that the active surface is inclined to the horizontal and, jetting the drops of encapsulant to form a bead of encapsulant material covering the series of wire bonds, the bead having a cross sectional profile that is asymmetrical about an axis parallel to a normal to the active surface.

Abstract translation: 在将微电子器件电连接到一系列导体的一系列引线键合上形成不对称密封剂珠的方法，该微电子器件具有平坦的有源表面。 该方法具有以下步骤：将管芯和引线接合在密封剂喷射器下方，将密封剂滴喷射到引线键合上，密封剂液滴沿垂直轨迹移动，倾斜模具使得活性表面倾斜于水平 并且，喷射所述密封剂滴以形成覆盖所述一系列引线接合的密封剂材料珠，所述珠具有围绕平行于所述活性表面的法线的轴线不对称的横截面轮廓。

公开(公告)号：US08003893B2

公开(公告)日：2011-08-23

申请号：US12145802

申请日：2008-06-25

Applicant: Hisao Miura ,  Shinji Murata

Inventor： Hisao Miura ,  Shinji Murata

IPC: H05K1/03

CPC classification number: H05K3/4007 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09781 ,  H05K2201/2009

Abstract: A multilayer ceramic circuit board includes ceramic wiring layers which are stacked together, one or two or more lifting layers which have a planar shape and which are disposed as an inner layer inside the stacked ceramic wiring layers or as a lower layer lower than a bottom ceramic wiring layer, and a protruding portion formed on a surface of a top ceramic wiring layer due to the disposition of the one or two or more lifting layers. The protruding portion smoothly protrudes and has a large area and high flatness. The multilayer ceramic circuit board is formed by disposing lifting layers as an inner layer of a plurality green sheets or as a lower layer lower than a bottom green sheet, and firing under pressure the resulting laminate in a state constrained by an elastic constraining sheet and a rigid constraining sheet.

Abstract translation: 多层陶瓷电路板包括堆叠在一起的陶瓷布线层，一个或两个以上的提升层，其具有平面形状，并且作为内层设置在堆叠的陶瓷布线层内部或作为比底部陶瓷 布线层和由于一个或两个或更多个提升层的布置而形成在顶部陶瓷布线层的表面上的突出部分。 突出部分平滑地突出并且具有大的面积和高的平坦度。 多层陶瓷电路板通过将提升层设置为多个生片的内层或低于底部生片的下层而形成，并且在受到弹性约束片约束的状态下在压力下烧结所得到的层压体， 刚性约束片。

公开(公告)号：US20110134314A1

公开(公告)日：2011-06-09

申请号：US13026279

申请日：2011-02-13

Applicant: WEN-HWA LIN ,  CHEN-KUANG YEH ,  XIANG HUANG ,  WAN-CHENG XIE ,  SHAO-GUANG MO

Inventor： WEN-HWA LIN ,  CHEN-KUANG YEH ,  XIANG HUANG ,  WAN-CHENG XIE ,  SHAO-GUANG MO

IPC: H04N5/225

CPC classification number: H04N5/2253 ,  H01L27/14618 ,  H01L2924/0002 ,  H04N5/2257 ,  H05K1/189 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/303 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/10121 ,  H05K2201/10727 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00

Abstract: An image sensor module includes a circuit board, an image sensor, and a supporting board. The image sensor is electrically connected to the circuit board. The circuit board defines a through opening therein. The supporting board is arranged on one side of the circuit board and includes a protrusion. The protrusion extends outwardly from the supporting board and includes a square-shaped block no larger than the image sensor. The square-shaped block passes through the through opening. The image sensor is mounted on the block and spaced from the circuit board.

Abstract translation: 图像传感器模块包括电路板，图像传感器和支撑板。 图像传感器电连接到电路板。 电路板在其中限定通孔。 支撑板布置在电路板的一侧并且包括突起。 突起从支撑板向外延伸并且包括不大于图像传感器的方形块。 方形块通过通孔。 图像传感器安装在块上并与电路板间隔开。

公开(公告)号：US07943859B2

公开(公告)日：2011-05-17

申请号：US10593796

申请日：2005-03-29

Applicant: Tsugio Ambo ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

Inventor： Tsugio Ambo ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

IPC: H01R12/04

CPC classification number: H05K3/202 ,  H01R9/2466 ,  H01R12/523 ,  H05K3/041 ,  H05K3/222 ,  H05K3/308 ,  H05K3/326 ,  H05K3/328 ,  H05K3/4046 ,  H05K3/4611 ,  H05K13/0061 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/091 ,  H05K2201/096 ,  H05K2201/10287 ,  H05K2201/10401 ,  H05K2201/1059 ,  H05K2201/10598 ,  H05K2203/081 ,  H05K2203/082 ,  H05K2203/167 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board with a simple structure is manufactured. A circuit board 19 has thereon a foil circuit 21 provided on a synthetic resin plate 20 formed by injection molding, made of a copper foil, and having a pattern different for circuit board 19. Anchor pins 20a projecting upward are provided on the resin plate 20 and passed through pinholes made in the foil circuit 21. The foil circuit 21 are positioned and secured to the resin plate 20. In a required portion of the resin plate 20, a terminal insertion hole 20c is provided, and receiving terminal 22 is secured to the required portion of the terminal insertion hole 20c and connected to the foil circuit 21.

Abstract translation: 制造具有简单结构的电路板。 电路板19上设置有箔电路21，该箔电路21设置在由铜箔制成的注塑成型的合成树脂板20上，并且具有不同于电路板19的图案。在树脂板20上设置有向上突出的锚定销20a 并通过箔片电路21中制成的针孔。箔片电路21定位并固定到树脂板20.在树脂板20的所需部分中，设置有端子插入孔20c，并且接收端子22固定到 端子插入孔20c的所需部分并连接到箔片电路21。

公开(公告)号：US07940220B2

公开(公告)日：2011-05-10

申请号：US12185341

申请日：2008-08-04

Applicant: Dae Seong Jeon ,  Sang Woo Bae ,  Jae Suk Sung

Inventor： Dae Seong Jeon ,  Sang Woo Bae ,  Jae Suk Sung

IPC: H01Q1/24

CPC classification number: H05K9/0045 ,  H05K1/0284 ,  H05K1/119 ,  H05K3/426 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09481 ,  H05K2201/0999

Abstract: There is provided a case structure having a conductive pattern and a method of manufacturing the same. A case structure having a conductive pattern according to an aspect of the invention includes a case having at least one via hole formed therein; at least conductive pattern formed on an outer surface of the case; and a conductive via formed within the via hole and electrically connecting the at least one conductive pattern to a board inside the case.

Abstract translation: 提供具有导电图案的壳体结构及其制造方法。 根据本发明的一个方面的具有导电图案的壳体结构包括：形成有至少一个通孔的壳体; 至少导电图案形成在外壳的外表面上; 以及形成在所述通孔内的导电通孔，并且将所述至少一个导电图案电连接到所述壳体内的板。

公开(公告)号：US20110034022A1

公开(公告)日：2011-02-10

申请号：US12905540

申请日：2010-10-15

Applicant: Junichi Nakamura

Inventor： Junichi Nakamura

IPC: H01L21/28

CPC classification number: H05K3/4007 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15159 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09481 ,  H05K2203/1536 ,  H01L2224/05552

Abstract: A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20) including a plurality of insulating resin layers, semiconductor element-mounting terminals (18) formed on the uppermost surface of the board, and external connection terminals (12) formed on the bottom surface thereof. Each external connection terminal (12) is formed as a bump projected downward from the bottom surface of the package, and each bump is filled with the insulating resin (14) while the surface thereof is covered by a metal (16). Wiring 124), (26) including a conductor via (26a) electrically connect the metal of the metal layer 16 and the semiconductor element-mounting terminals (18).

Abstract translation: 公开了一种半导体封装及其制造方法，通过使用包含较少量的引线的外部连接端子或半导体元件安装端子，同时实现端子的精细间距来解决环境问题。 半导体封装包括：多个绝缘树脂层的基板（20），形成在基板的最上表面上的半导体元件安装端子（18）和形成在其底面上的外部连接端子（12）。 每个外部连接端子（12）形成为从封装的底表面向下突出的凸起，并且每个凸起都填充有绝缘树脂（14），同时其表面被金属（16）覆盖。 包括导体通孔（26a）的布线124），（26）将金属层16的金属与半导体元件安装端子（18）电连接。