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    EMBEDDED CAPACITOR MODULE
    33.
    发明申请
    EMBEDDED CAPACITOR MODULE 有权
    嵌入式电容器模块

    公开(公告)号：US20130248235A1

    公开(公告)日：2013-09-26

    申请号：US13896436

    申请日：2013-05-17

    Applicant: Industrial Technology Research Institute

    Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Cheng-Liang Cheng ,  Li-Duan Tsai

    IPC: H05K1/18

    CPC classification number: H05K1/185 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/4608 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2203/0315

    Abstract: An embedded capacitor module includes an electrode lead-out portion and at least one solid electrolytic capacitor portion adjacently disposed with the electrode lead-out portion. The electrode lead-out portion comprises a first substrate, a second substrate, a first insulating material disposed between the first substrate and the second substrate, a first porous layer formed on at least one surface of the first substrate, and a first oxide layer disposed on the first porous layer. The solid electrolytic capacitor portion comprises the first substrate, the second substrate, the first porous layer, the first oxide layer, all of which are extended from the electrode lead-out portion, a first conductive polymer layer disposed on the first oxide layer, a first carbon layer disposed on the first conductive polymer layer, and a first conductive adhesive layer disposed on the first carbon layer.

    Abstract translation: 嵌入式电容器模块包括电极引出部分和与电极引出部分相邻设置的至少一个固体电解电容器部分。 电极引出部包括第一基板，第二基板，设置在第一基板和第二基板之间的第一绝缘材料，形成在第一基板的至少一个表面上的第一多孔层和设置在第一基板 在第一多孔层上。 固体电解电容器部分包括第一衬底，第二衬底，第一多孔层，第一氧化物层，它们全部从电极引出部分延伸出来，第一导电聚合物层设置在第一氧化物层上， 设置在第一导电聚合物层上的第一碳层和设置在第一碳层上的第一导电粘合剂层。

    Wiring member and method for producing the same
    34.
    发明授权
    Wiring member and method for producing the same 有权
    接线构件及其制造方法

    公开(公告)号：US08541686B2

    公开(公告)日：2013-09-24

    申请号：US12444773

    申请日：2009-04-08

    Applicant: Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga ,  Mitsuaki Negishi

    Inventor： Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga ,  Mitsuaki Negishi

    IPC: H05K1/03 ,  H05K3/36

    CPC classification number: H05K1/09 ,  H05K1/0216 ,  H05K1/0234 ,  H05K1/167 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0326 ,  H05K2201/09309

    Abstract: A wiring member including: a copper foil; a noise suppressing layer containing a metallic material or a conductive ceramic and having a thickness within the range of 5 to 200 nm; an organic polymer film; and an insulating adhesive layer, wherein the insulating adhesive layer is provided between the organic polymer film formed on the noise suppressing layer and the copper foil, or between the noise suppressing layer formed on the organic polymer film and the copper foil. Further, there is provided a method for producing the wiring member.

    Abstract translation: 一种布线构件，包括：铜箔; 含有金属材料或导电陶瓷的噪声抑制层，其厚度在5〜200nm的范围内; 有机聚合物膜; 绝缘性粘合剂层，其中，所述绝缘粘合剂层设置在形成在所述噪声抑制层上的有机聚合物膜与所述铜箔之间或所述有机聚合物膜上形成的噪声抑制层与所述铜箔之间。 此外，提供了一种制造布线构件的方法。

    Multilayer substrate
    35.
    发明授权
    Multilayer substrate 有权
    多层基板

    公开(公告)号：US08536464B2

    公开(公告)日：2013-09-17

    申请号：US12994774

    申请日：2008-05-26

    Applicant: Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

    Inventor： Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

    IPC: H05K1/11

    CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

    Abstract: A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

    Abstract translation: 多层基板设置有布置有多个导体平面的导体平面区域; 与所述导体平面区域相邻设置的间隙区域，以使所述多个导体平面从所述间隙区域排除。 多个信号通孔设置穿过间隙区域，使得多个信号通孔与多个导体平面隔离。 导体柱连接到多个导体平面中的一个并且设置在间隙区域中的两个信号通孔之间。

    Method of forming multilayer capacitors in a printed circuit substrate
    36.
    发明授权
    Method of forming multilayer capacitors in a printed circuit substrate 有权
    在印刷电路基板中形成多层电容器的方法

    公开(公告)号：US08501575B2

    公开(公告)日：2013-08-06

    申请号：US12909983

    申请日：2010-10-22

    Applicant: Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    Inventor： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    IPC: H01G4/00

    CPC classification number: H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

    Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

    Abstract translation: 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

    Methods of embedding thin-film capacitors into semiconductor packages using temporary carrier layers
    38.
    发明授权
    Methods of embedding thin-film capacitors into semiconductor packages using temporary carrier layers 有权
    使用临时载体层将薄膜电容器嵌入半导体封装的方法

    公开(公告)号：US08409963B2

    公开(公告)日：2013-04-02

    申请号：US12763412

    申请日：2010-04-20

    Applicant: Lynne E. Dellis ,  Karl Hartmann Dietz ,  David Ross McGregor

    Inventor： Lynne E. Dellis ,  Karl Hartmann Dietz ,  David Ross McGregor

    IPC: H01L51/05 ,  H01L29/92

    CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K3/025 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/083 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09718 ,  H05K2201/10674 ,  H05K2203/104

    Abstract: Disclosed are methods of making a semiconductor package comprising at least one thin-film capacitor embedded into at least one build-up layer of said semiconductor package. A thin-film capacitor is provided wherein the thin-film capacitor has a first electrode and a second electrode separated by a dielectric. A temporary carrier layer is applied to the first electrode and the second electrode is patterned. A PWB core and a build-up material are provided, and the build-up material is placed between the PWB core and the patterned second electrode of said thin-film capacitor. The patterned electrode side of the thin-film capacitor is laminated to the PWB core by way of the build-up material, the temporary carrier layer is removed, and the first electrode is patterned.

    Abstract translation: 公开了制造半导体封装的方法，该半导体封装包括嵌入到所述半导体封装的至少一个堆积层中的至少一个薄膜电容器。 提供了一种薄膜电容器，其中薄膜电容器具有由电介质隔开的第一电极和第二电极。 临时载体层被施加到第一电极并且第二电极被图案化。 提供PWB芯和堆积材料，并且积聚材料被放置在PWB芯和所述薄膜电容器的图案化的第二电极之间。 薄膜电容器的图案化电极侧通过积聚材料层叠到PWB芯上，去除临时载体层，并对第一电极进行图案化。

    Electromagnetic bandgap structure and printed circuit board
    40.
    发明授权
    Electromagnetic bandgap structure and printed circuit board 有权
    电磁带隙结构和印刷电路板

    公开(公告)号：US08368488B2

    公开(公告)日：2013-02-05

    申请号：US12155941

    申请日：2008-06-11

    Applicant: Han Kim ,  Hyung-Sik Choi ,  Sang-Hoon Kim ,  Joon-Sung Kim

    Inventor： Han Kim ,  Hyung-Sik Choi ,  Sang-Hoon Kim ,  Joon-Sung Kim

    IPC: H01P1/203

    CPC classification number: H05K1/116 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09627 ,  H01L2224/0401

    Abstract: An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment of the present invention, an electromagnetic bandgap structure is stacked with a first metal layer, a first dielectric layer, a metal plate, a second dielectric layer and a second metal layer, and an odd number of vias can be serially connected through a metal line between the first metal layer and the metal plate. This electromagnetic bandgap structure can have a small size and a low bandgap frequency.

    Abstract translation: 公开了可解决模拟电路和数字电路之间的混合信号问题的电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构层叠有第一金属层，第一介电层，金属板，第二介电层和第二金属层，并且可以串联奇数个通孔 通过第一金属层和金属板之间的金属线连接。 该电磁带隙结构可以具有小尺寸和低带隙频率。

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