公开(公告)号：US20150043184A1

公开(公告)日：2015-02-12

申请号：US14453146

申请日：2014-08-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Koichi Odagaki ,  Shuichi Kato

IPC: H05K3/34 ,  H05K1/11

CPC classification number: H05K1/111 ,  H01L2924/15313 ,  H05K2201/09381 ,  H05K2201/099 ,  Y02P70/611

Abstract: A circuit substrate which is capable of decreasing the possibility that the amount of solder in the overall mounting land is uneven and reducing formation of a solder void even when a mounting terminal has a large soldering area. An electronic component having the mounting terminal is mounted on the circuit substrate. A mounting land is connected to the mounting terminal of the electronic component by soldering, and the mounting land has a protruding portion of an insulating material formed so as to protrude from an outer side of the mounting land toward an inner side of the mounting land, and the protruding portion does not divide the mounting land into a plurality of areas.

Abstract translation: 电路基板能够降低整个安装台面中的焊料的量不均匀的可能性，并且即使在安装端子具有大的焊接区域的情况下也减少形成焊料空隙。 具有安装端子的电子部件安装在电路基板上。 安装平台通过焊接连接到电子部件的安装端子，并且安装台面具有形成为从安装台面的外侧向安装台面的内侧突出的绝缘材料的突出部， 并且突出部分不将安装平台分成多个区域。

公开(公告)号：US20140318842A1

公开(公告)日：2014-10-30

申请号：US13952573

申请日：2013-07-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Byung Woo HAN ,  Dae Bok OH ,  Jae Yeol CHOI ,  Sang Huk KIM

IPC: H01G4/30 ,  H05K1/18 ,  H01G2/06

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/012 ,  H01G4/232 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: There is provided a multilayer ceramic electronic component includes: a ceramic body including dielectric layers stacked therein and satisfying T(thickness)/W(width)>1.0; first and second internal electrodes disposed to face each other in the ceramic body, having the dielectric layer disposed therebetween, and alternately exposed through end surfaces of the ceramic body; and first and second external electrodes extended from the end surfaces of the ceramic body to upper and lower main surfaces of the ceramic body wherein, when a height of the ceramic body is defined as a, and a distance from an upper end of the first or second external electrode formed on the upper main surface of the ceramic body to a lower end of the first or second external electrode formed on the lower main surface of the ceramic body is defined as b, 0.990≦a/b

Abstract translation: 提供了一种多层陶瓷电子部件，包括：陶瓷体，其包含堆叠在其中且满足T（厚度）/ W（宽度）> 1.0的电介质层; 第一和第二内部电极，其设置在陶瓷体中彼此面对，其间具有介电层，并且通过陶瓷体的端面交替暴露; 以及第一外部电极和第二外部电极，其从陶瓷体的端面延伸到陶瓷体的上部和下部主表面，其中当陶瓷体的高度被限定为a，并且距离第一或 形成在陶瓷体的上主表面上的形成在陶瓷体的下主表面上的第一或第二外部电极的下端的第二外部电极被定义为b，0.990＆nlE; a / b <1。

公开(公告)号：US08796558B2

公开(公告)日：2014-08-05

申请号：US13497831

申请日：2011-03-24

Applicant: Minoru Iizuka ,  Yuka Kojo

Inventor： Minoru Iizuka ,  Yuka Kojo

IPC: H05K5/00

CPC classification number: H05K5/0091 ,  H01L23/053 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/15162 ,  H01L2924/16195 ,  H03H9/1021 ,  H05K3/3431 ,  H05K3/3442 ,  H05K5/0095 ,  H05K2201/09381 ,  H05K2201/10068 ,  H05K2201/10075 ,  Y02P70/613 ,  H01L2924/00

Abstract: A base of a surface-mount electronic component package holds an electronic component element and is to be mounted on a circuit board with a conductive bonding material. The base has a principal surface and an external connection terminal to be electrically connected to the circuit board. The external connection terminal is formed in the principal surface. The base includes a bump formed on the external connection terminal. The bump is smaller than the external connection terminal. The base has a distance d between an outer periphery end edge of the external connection terminal and an outer periphery end edge of the bump along an attenuating direction of stress on the external connection terminal The stress is generated in association of mounting of the base on the circuit board. The distance d is more than 0.00 mm and equal to or less than 0.45 mm.

Abstract translation: 表面安装电子部件封装的基座保持电子元件，并且将被安装在具有导电接合材料的电路板上。 基座具有主电路表面和与电路板电连接的外部连接端子。 外部连接端子形成在主面上。 底座包括形成在外部连接端子上的凸块。 凸块小于外部连接端子。 底座在外部连接端子的应力的衰减方向上具有外部连接端子的外周端边缘与突起的外周端边缘之间的距离d。 电路板。 距离d大于0.00mm且等于或小于0.45mm。

公开(公告)号：US20140138140A1

公开(公告)日：2014-05-22

申请号：US14082574

申请日：2013-11-18

Applicant: MAGNA ELECTRONICS INC.

Inventor： Marc Sigle

IPC: H05K1/11

CPC classification number: H05K1/111 ,  B60R1/00 ,  B60R2300/8066 ,  G06K9/00805 ,  H04N7/183 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/09418 ,  Y02P70/611

Abstract: A circuit board for an image processing chip of a vision system of a vehicle is configured for a surface mount device to be attached thereto and includes at least one mounting location having a plurality of solder pads established thereat. The pads are arranged in a manner that enhances soldering of the device or component to the pad and circuit board. The pads may be arranged similarly in respective portions of the mounting location, such that the pads of one portion of the mounting location may be generally parallel to one another and may be generally orthogonal to the pads of another portion of the mounting location. Optionally, the pads may be generally tear-drop shaped, and the tear-drop shaped pads may be arranged so as to point generally towards or generally away from a center area of the mounting location of the circuit board.

Abstract translation: 用于车辆视觉系统的图像处理芯片的电路板被配置为用于附接到其上的表面安装装置，并且包括至少一个安装位置，该安装位置具有在其上建立的多个焊盘。 焊盘以增强器件或部件对焊盘和电路板的焊接的方式布置。 垫可以类似地布置在安装位置的相应部分中，使得安装位置的一部分的焊盘可以大体上彼此平行并且可以大致垂直于安装位置的另一部分的焊盘。 可选地，垫可以通常为泪滴形状，并且泪滴形垫可以被布置成大致朝向或大体上远离电路板的安装位置的中心区域。

公开(公告)号：US20140077896A1

公开(公告)日：2014-03-20

申请号：US14027835

申请日：2013-09-16

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Dong Hwan LEE ,  Seung Wook Park ,  Christian Romero ,  Young Do Kweon ,  Jin Gu Kim

IPC: H03H7/01

CPC classification number: H03H7/17 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09381

Abstract: The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided.

Abstract translation: 本发明涉及具有开口短截线的通孔结构和具有该开口短路的印刷电路板。 根据本发明的实施例，具有开口短截线的通孔结构包括：通过绝缘层的信号传输; 用于连接分别形成在绝缘层上和下面的第一和第二传输线的上和下通孔焊盘和信号传输通孔; 并且提供连接到每个通孔焊盘的外周的至少一个开放短截线以具有形成在绝缘层上和下面的每个接地图案的分流电容。 此外，提供了具有开口短路的通孔的印刷电路板。

公开(公告)号：US20140055965A1

公开(公告)日：2014-02-27

申请号：US14069402

申请日：2013-11-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromichi KITAJIMA

IPC: H05K1/02 ,  H05K7/06 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4629 ,  H05K7/06 ,  H05K2201/09381 ,  H05K2201/0979 ,  H05K2201/099 ,  H01L2924/00

Abstract: A via conductor connected to a mounting electrode near a corner portion of a circuit substrate is provided in a position in a corresponding mounting electrode, located closer to the center of the circuit substrate. Thus, concentration of a stress in a portion of the via conductor is effectively reduced, and a break, a chip, or a crack is prevented from occurring to the circuit substrate. Even if the portion located closer to the corner portion of the mounting electrode is peeled from the circuit substrate, the electrical characteristics of the circuit module are secured because disconnection between the corresponding mounting electrode and the via conductor is prevented.

Abstract translation: 连接到电路基板的角部附近的安装电极的通孔导体设置在位于更靠近电路基板的中心的相应的安装电极的位置。 因此，有效地减小了通路导体的一部分中的应力集中，并且防止了对电路基板的破裂，芯片或裂纹的发生。 即使靠近安装电极的角部的部分从电路基板剥离，也可以确保电路模块的电气特性，因为防止了相应的安装电极和通路导体之间的断开。

公开(公告)号：US20140042320A1

公开(公告)日：2014-02-13

申请号：US13569898

申请日：2012-08-08

Applicant: Gerhard Knaup ,  Fred Plotz

Inventor： Gerhard Knaup ,  Fred Plotz

IPC: G01J5/10 ,  H05K3/00

CPC classification number: G01J5/34 ,  G01J5/0285 ,  G01J2001/0276 ,  H05K1/0224 ,  H05K1/023 ,  H05K1/112 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10151 ,  H05K2201/10166 ,  Y10T29/49155

Abstract: A circuit for detecting electromagnetic radiation includes a pyroelectric sensor element connected to convert electromagnetic radiation into an electric signal. An n-channel junction field effect transistor is connected to receive the electric signal. A printed circuit board includes at least one low inductance low resistance area to provide a ground path for all alternating current components. A first capacitor is connected between the FET source terminal and a second capacitor is connected between the FET drain terminal and ground. A gate resistor is connected in parallel with the sensor element or a resistor is included in the sensor elements.

Abstract translation: 用于检测电磁辐射的电路包括被连接以将电磁辐射转换成电信号的热电传感器元件。 n沟道结场效应晶体管被连接以接收电信号。 印刷电路板包括至少一个低电感低电阻区域，以为所有交流分量提供接地路径。 第一电容器连接在FET源极端子之间，第二电容器连接在FET漏极端子和地之间。 栅极电阻器与传感器元件并联连接，或者传感器元件中包含电阻器。

公开(公告)号：US20140041914A1

公开(公告)日：2014-02-13

申请号：US13959949

申请日：2013-08-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo HATTORI ,  Isamu FUJIMOTO

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01G2/065 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2036 ,  H05K2201/2045 ,  Y02P70/611 ,  Y02P70/613

Abstract: A mounting land structure and a mounting structure include land patterns to be bonded to outer electrodes of a laminated ceramic capacitor. Each of the land patterns includes a first conductor pattern and a second conductor pattern separated from each other in a width direction and a third conductor pattern connecting the first conductor pattern and the second conductor pattern. The first conductor pattern and the second conductor pattern include respective portions to be bonded to first ridgeline portions of the laminated ceramic capacitor provided with the outer electrodes. The third conductor pattern is arranged at a position overlapping the corresponding outer electrode as viewed in a height direction, when the laminated ceramic capacitor is mounted.

Abstract translation: 安装平台结构和安装结构包括与层压陶瓷电容器的外部电极接合的焊盘图案。 每个焊盘图案包括在宽度方向上彼此分离的第一导体图案和第二导体图案，以及连接第一导体图案和第二导体图案的第三导体图案。 第一导体图案和第二导体图案包括要被接合到设置有外部电极的层叠陶瓷电容器的第一脊线部分的各个部分。 当安装层叠陶瓷电容器时，第三导体图案被布置在与高度方向相对的相应的外部电极重叠的位置。

公开(公告)号：US20120295454A1

公开(公告)日：2012-11-22

申请号：US13564483

申请日：2012-08-01

Applicant: Zhiwei Jiang ,  Xiaochen Chen ,  Zhipeng Guo

Inventor： Zhiwei Jiang ,  Xiaochen Chen ,  Zhipeng Guo

IPC: H01R12/51

CPC classification number: H05K1/111 ,  H05K1/112 ,  H05K1/141 ,  H05K3/225 ,  H05K2201/09072 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09663 ,  H05K2203/042 ,  Y02P70/611

Abstract: A printed circuit board assembly (PCBA) chip package component includes: a module board and an interface board. A first soldering pad is set on the bottom of the module board, a second soldering pad is set on top of the interface board, and the second soldering pad is of a castle-type structure. The first soldering pad includes a first soldering area, a second soldering area, and a connection bridge that connects the first soldering area and the second soldering area. The first soldering area corresponds to a top surface of the second soldering pad, and when the first soldering area is soldered to second soldering pad, the second soldering area is located outside the second soldering pad.

Abstract translation: 印刷电路板组件（PCBA）芯片封装组件包括：模块板和接口板。 第一个焊盘设置在模块板的底部，第二个焊盘设置在接口板的顶部，第二个焊盘为城堡式结构。 第一焊盘包括第一焊接区域，第二焊接区域和连接第一焊接区域和第二焊接区域的连接桥。 第一焊接区域对应于第二焊盘的顶表面，并且当第一焊接区域焊接到第二焊盘时，第二焊接区域位于第二焊盘的外部。

公开(公告)号：US20120287016A1

公开(公告)日：2012-11-15

申请号：US13467076

申请日：2012-05-09

Applicant: Beata Zalinska ,  Oliver Paul Leisten

Inventor： Beata Zalinska ,  Oliver Paul Leisten

IPC: H01Q1/36 ,  H01P11/00

CPC classification number: H01Q11/08 ,  H01Q1/38 ,  H01Q1/40 ,  H05K1/11 ,  H05K1/182 ,  H05K2201/09027 ,  H05K2201/09381 ,  H05K2201/10098 ,  H05K2203/0574 ,  Y10T29/49016

Abstract: A method of manufacturing a dielectrically loaded antenna having an operating frequency in excess of 200 MHz, the antenna having an electrically insulative core, the method including steps of: forming a first patterned layer of conductive material having a plurality of inner conductive tracks on at least one surface of the core of the antenna; depositing a layer of insulative material over at least a portion of the first layer of conductive material; and forming a second patterned layer of conductive material having a plurality of outer conductive tracks, at least partially overlapping the inner conductive tracks.

Abstract translation: 一种制造具有超过200MHz的工作频率的介电加载天线的方法，所述天线具有电绝缘芯，所述方法包括以下步骤：至少形成具有多个内部导电轨道的导电材料的第一图案化层 天线核心的一个表面; 在所述第一导电材料层的至少一部分上沉积绝缘材料层; 以及形成具有至少部分地与所述内部导电轨道重叠的多个外部导电轨道的导电材料的第二图案化层。