公开(公告)号：US20120175158A1

公开(公告)日：2012-07-12

申请号：US13427328

申请日：2012-03-22

Applicant: Taiji OGAWA

Inventor： Taiji OGAWA

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K1/111 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A circuit board 1 comprises: an insulating substrate 10; and electric circuit patterns 20 formed on the insulating substrate 10. Each electric circuit pattern 20 has: a mounting pad section 30; and a wiring section 40 extending from the mounting pad section 30. The mounting pad section 30 has a first nonparallel surface 32a inclined to or substantially orthogonally intersecting a main surface 41 of the wiring section 40.

Abstract translation: 电路板1包括：绝缘基板10; 和形成在绝缘基板10上的电路图案20.每个电路图案20具有：安装焊盘部分30; 以及从安装焊盘部分30延伸的布线部分40.安装焊盘部分30具有与布线部分40的主表面41倾斜或基本上垂直相交的第一非平行表面32a。

公开(公告)号：US08212149B2

公开(公告)日：2012-07-03

申请号：US12041916

申请日：2008-03-04

Applicant: Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

Inventor： Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/16

CPC classification number: H05K1/0224 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract translation: 提供传输线的磁场分布和互电容控制。 通过将参考平面层附着到介电材料层并且将第一迹线附接到电介质材料的第二表面来制造第一电路板。 修改参考平面层的表面轮廓以减小通过参考平面层的返回电流信号路径的电阻，以减小第一迹线和第二迹线之间的磁场耦合。 通过将参考平面层附着到电介质材料层，将迹线附着到电介质材料上，以及在迹线上的介电材料层上形成焊料掩模层来制造第二电路板。 修改焊接掩模层的有效介电常数以减小或增加介电材料上的第一迹线和第二迹线之间的互电容。

公开(公告)号：US08171630B2

公开(公告)日：2012-05-08

申请号：US12047603

申请日：2008-03-13

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R43/16

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure includes mounting at least one interposer on a first surface of an electrically insulating carrier plane. The interposer selectively having a hemi-toroidal, conical, dome-shaped conic section, generally cylindrical or hemi-spherical configuration in transverse cross-section and being constituted of a dielectric elastomeric material. The method includes positioning a plurality of electrically-conductive elements about the surface of the hemi-toroidal interposer that extend radially inwardly and downwardly from an uppermost end thereof. The method further includes mounting said at least one component comprising at least one hemi-toroidal interposer mounted on said opposite side of said carrier plane. Additionally the method includes forming at least one through-extending via in said electrically-insulating carrier plane, and forming electrical connections between said first-mentioned at least one hemi-toroidal interposer and said further at least one inverted hemi-toroidal interposer.

Abstract translation: 一种制造焊盘格栅阵列（LGA）插入器结构的方法包括在电绝缘载体平面的第一表面上安装至少一个插入件。 中间层选择性地具有半环形，圆锥形的圆顶形圆锥形截面，横截面为大致圆柱形或半球形，并由介电弹性体材料构成。 该方法包括围绕半环形插入器的表面定位多个导电元件，其从其最上端径向向内和向下延伸。 该方法还包括安装所述至少一个部件，该部件包括安装在所述载体平面的相对侧上的至少一个半环形插入器。 另外，该方法包括在所述电绝缘载体平面中形成至少一个贯通孔，以及在所述第一提到的至少一个半环形插入件与所述另外的至少一个反向半环形插入件之间形成电连接。

公开(公告)号：US20120069543A1

公开(公告)日：2012-03-22

申请号：US12886970

申请日：2010-09-21

Applicant: YAN-HUA CHEN

Inventor： YAN-HUA CHEN

IPC: F21V9/16 ,  H01L21/56

CPC classification number: F21V29/51 ,  F21K9/00 ,  F21K9/90 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L23/24 ,  H01L24/45 ,  H01L25/0753 ,  H01L33/648 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/01047 ,  H01L2924/12041 ,  H01L2924/181 ,  H05K1/0272 ,  H05K2201/09745 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An LED illuminator module with high heat-dissipating efficiency and manufacturing method therefor is provided. The LED illuminator module includes a flat heat pipe (FHP) formed with a flat surface, an insulated layer formed on the plane of the flat heat pipe, a conducting layer having a pair of conducting electrode portions, a plurality of LEDs, and an encapsulation covers the LEDs. The insulation layer has a pair of insulated electrode portions and a plurality of LED-setting portions. The conducting electrode portions partially covered on the insulated electrode portions. The LEDs are disposed on the LED-setting portions and electrically connect to the pair of conducting electrode portions respectively. The encapsulation contains phosphor powder therein. The present invention solves the heat-dissipating problem of high-efficiency light module with the LEDs, and shorten heat-conductive path to enhance heat-dissipating efficiency.

Abstract translation: 提供了具有高散热效率的LED照明器模块及其制造方法。 LED照明器模块包括形成有平坦表面的平坦热管（FHP），形成在平坦热管的平面上的绝缘层，具有一对导电电极部分，多个LED以及封装的导电层 覆盖LED。 绝缘层具有一对绝缘电极部分和多个LED设置部分。 导电电极部分被部分覆盖在绝缘电极部分上。 LED设置在LED设置部分上并分别电连接到一对导电电极部分。 封装中含有荧光体粉末。 本发明解决了LED的高效率光模块的散热问题，缩短了导热路径，提高了散热效率。

公开(公告)号：US20110303440A1

公开(公告)日：2011-12-15

申请号：US12900226

申请日：2010-10-07

Applicant: Chang Hyun LIM ,  Jung Eun KANG ,  Heung Soo PARK ,  Seog Moon CHOI ,  Kwang Soo KIM ,  Joon Seok CHAE ,  Sung Keun PARK

Inventor： Chang Hyun LIM ,  Jung Eun KANG ,  Heung Soo PARK ,  Seog Moon CHOI ,  Kwang Soo KIM ,  Joon Seok CHAE ,  Sung Keun PARK

IPC: H05K1/03 ,  H05K3/44 ,  C23C28/00

CPC classification number: H05K3/10 ,  H05K1/0203 ,  H05K1/053 ,  H05K3/108 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/062 ,  H05K2201/09745 ,  H05K2201/10166 ,  H05K2203/0315 ,  Y10T29/4913

Abstract: Disclosed herein are a hybrid heat-radiating substrate including a metal core layer; an oxide insulating core layer that is formed in a thickness direction of the metal core layer to have a shape where the oxide insulating core layer is integrally formed with the metal core layer, an oxide insulating layer that is formed on one surface or both surfaces of the metal core layer, and a circuit layer that is configured to include first circuit patterns formed on the oxide insulating core layer and second circuit patterns formed on the oxide insulating layer, and a method of manufacturing the same.

Abstract translation: 本文公开了包括金属芯层的混合散热基板; 氧化物绝缘芯层，其形成在所述金属芯层的厚度方向上，以形成所述氧化物绝缘芯层与所述金属芯层一体形成的形状;氧化物绝缘层，其形成在所述金属芯层的一个表面或两个表面上 金属芯层，以及被配置为包括形成在氧化物绝缘芯层上的第一电路图案和形成在氧化物绝缘层上的第二电路图案的电路层及其制造方法。

公开(公告)号：US20110284278A1

公开(公告)日：2011-11-24

申请号：US13110136

申请日：2011-05-18

Applicant: Kiyohiro Hine ,  Shigeaki Sakatani ,  Akio Furusawa

Inventor： Kiyohiro Hine ,  Shigeaki Sakatani ,  Akio Furusawa

IPC: H05K1/18

CPC classification number: H05K1/111 ,  H05K3/3442 ,  H05K3/3484 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09663 ,  H05K2201/09745 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A mounting structure includes an insulating substrate having a substrate electrode on which at least one electrode notch is provided and a resist, an electronic component having an electronic component electrode to be electrically connected to the substrate electrode, and solder paste printed on a surface of the substrate electrode. The substrate electrode has a following relation, 0

Abstract translation: 安装结构包括绝缘基板，其具有设置有至少一个电极切口的基板电极和抗蚀剂，具有电连接到基板电极的电子部件电极的电子部件和印刷在基板电极的表面上的焊膏 基板电极。 基板电极具有以下关系：0

公开(公告)号：US20110198112A1

公开(公告)日：2011-08-18

申请号：US12874013

申请日：2010-09-01

Applicant: Kwang Soo KIM ,  Ki Ho SEO

Inventor： Kwang Soo KIM ,  Ki Ho SEO

IPC: H05K1/09 ,  H01B13/00

CPC classification number: H05K1/053 ,  H05K3/06 ,  H05K3/062 ,  H05K2201/09745 ,  H05K2203/0315 ,  H05K2203/0369

Abstract: Disclosed herein is a method for manufacturing a printed circuit board, including: (A) preparing an aluminum substrate; (B) patterning and etching an etching resist on the aluminum substrate; (C) forming an insulating layer by performing an anodizing treatment on the patterned aluminum substrate; and (D) forming a metal wiring layer by removing the etching resist. The aluminum wiring and the insulating layer are simultaneously formed on the surface of the aluminum patterned by etching through an anodizing method, thereby simplifying the manufacturing process of the substrate and improving adhesion between the metal wiring layer and the insulating layer. In addition, the thickness of the insulating layer and the thickness of the metal wiring layer can be controlled by controlling the anodizing treatment time, thereby providing a method for manufacturing a printed circuit board that can be manufactured to fit for use purpose.

Abstract translation: 本发明公开了一种印刷电路板的制造方法，包括：（A）制备铝基板; （B）在铝基板上图案化和蚀刻抗蚀剂; （C）通过对图案化的铝基板进行阳极氧化处理来形成绝缘层; 和（D）通过除去抗蚀剂形成金属布线层。 通过阳极氧化法通过蚀刻同时形成铝布线和绝缘层，从而简化了基板的制造工艺，提高了金属布线层与绝缘层之间的密合性。 此外，可以通过控制阳极化处理时间来控制绝缘层的厚度和金属布线层的厚度，从而提供可以制造成适合用途的印刷电路板的制造方法。

公开(公告)号：US07994428B2

公开(公告)日：2011-08-09

申请号：US12335449

申请日：2008-12-15

Applicant: Kuo-Ching Tsai ,  Chang-fu Lin Chang

Inventor： Kuo-Ching Tsai ,  Chang-fu Lin Chang

IPC: H01L23/48 ,  H05K1/03

CPC classification number: H05K1/111 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/161 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2924/0002 ,  H01L2924/01033 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/05552

Abstract: An electronic carrier board for a chip to be mounted thereon is provided, which includes a body and a plurality of solder pads. The solder pads have carrying surfaces for carrying the chip thereon through conductive bumps. The carrying surfaces of at least two solder pads are oppositely inclined with respect to each other, thereby preventing the conductive bumps mounted on the carrying surfaces from displacement and thereby further preventing two adjacent conductive bumps subject to displacement from coming into short-circuit contact.

Abstract translation: 提供一种用于安装在其上的芯片的电子载板，其包括主体和多个焊盘。 焊盘具有用于通过导电凸块承载芯片的承载表面。 至少两个焊盘的承载表面相对于彼此相对地倾斜，从而防止安装在承载表面上的导电凸块的位移，从而进一步防止两个相邻的导电凸块经受位移而进入短路接触。

公开(公告)号：US07992291B2

公开(公告)日：2011-08-09

申请号：US11976070

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K3/20 ,  H05K1/18

CPC classification number: H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.

Abstract translation: 一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。 利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。

公开(公告)号：US07964957B2

公开(公告)日：2011-06-21

申请号：US12342363

申请日：2008-12-23

Applicant: Mitsuru Noguchi ,  Sadamichi Takakusaki

Inventor： Mitsuru Noguchi ,  Sadamichi Takakusaki

IPC: H01L23/24

CPC classification number: H05K1/05 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/19105 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/44 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09745 ,  H05K2203/1572 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A semiconductor device that includes a metal substrate including a top surface, a bottom surface and four side surfaces, a conductive pattern insulated from the metal substrate, and a semiconductor element mounted on and electrically connected to the conductive pattern. The top surface is insulated. Each of the side surfaces of the metal substrate includes a first inclining side surface and a second inclining side surface so as to form a convex shape protruding outwardly between the top surface and the bottom surface of the metal substrate, and the first inclining side surfaces of a pair of two opposing side surfaces are smaller than corresponding first inclining side surfaces of another pair of two opposing side surfaces.

Abstract translation: 一种包括金属基板的半导体器件，包括顶表面，底表面和四个侧表面，与金属基板绝缘的导电图案，以及安装在导电图案上并电连接到导电图案的半导体元件。 顶面绝缘。 金属基板的每个侧表面包括第一倾斜侧表面和第二倾斜侧表面，以便形成在金属基板的顶表面和底表面之间向外突出的凸形，并且第一倾斜侧表面 一对两个相对的侧表面小于另一对相对侧表面的相应的第一倾斜侧表面。