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    PCB connector
    31.
    发明申请
    PCB connector 有权
    PCB连接器

    公开(公告)号：US20140315398A1

    公开(公告)日：2014-10-23

    申请号：US14248888

    申请日：2014-04-09

    Applicant: Knuerr GmbH

    Inventor： Josef FEIGL

    IPC: H01R12/70

    CPC classification number: H01R12/7082 ,  H01R12/523 ,  H01R12/585 ,  H05K1/113 ,  H05K1/144 ,  H05K3/368 ,  H05K3/40 ,  H05K2201/042 ,  H05K2201/09863 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2201/10878

    Abstract: The invention relates to a PCB connector for fastening a first printed circuit board on a second printed circuit board. The PCB connector may have a longitudinal base body with a clamping and fastening device for tool-free fastening of the PCB connector on a printed circuit board. The clamping and fastening device has a put-through body and a spring body which is formed extendable upon putting-through the put-through body through the land. The base body is thus pressed against the printed circuit board by the spring body.

    Abstract translation: 本发明涉及一种用于将第一印刷电路板固定在第二印刷电路板上的PCB连接器。 PCB连接器可以具有带有夹紧和紧固装置的纵向基体，用于将PCB连接器无缝地固定在印刷电路板上。 夹紧和紧固装置具有穿透体和弹簧体，弹性体在穿过穿过体穿过脊部时形成为可延伸的。 基体因此被弹簧体压靠在印刷电路板上。

    MULTI-PIECE-ARRAY AND METHOD OF MANUFACTURING THE SAME
    32.
    发明申请
    MULTI-PIECE-ARRAY AND METHOD OF MANUFACTURING THE SAME 有权
    多组块和其制造方法

    公开(公告)号：US20130183475A1

    公开(公告)日：2013-07-18

    申请号：US13876670

    申请日：2011-09-30

    Applicant: Yoshitaka Yoshida ,  Hiroaki Yamamoto

    Inventor： Yoshitaka Yoshida ,  Hiroaki Yamamoto

    IPC: H05K1/03 ,  B32B3/30 ,  H05K3/00

    CPC classification number: H05K1/0306 ,  B32B3/30 ,  H05K1/09 ,  H05K3/00 ,  H05K3/0052 ,  H05K3/0097 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09863 ,  Y10T156/10 ,  Y10T428/15

    Abstract: A multi-piece-array formed by laminating a plurality of ceramic layers includes: a product region where a plurality of wiring board portions having a rectangular shape in plan view and including cavities are arranged in matrix; a redundant portion that is positioned along a periphery of the product region; and dividing grooves that are formed on a front surface and/or a back surface along a boundary between the wiring board portions and a boundary between the wiring board portion and the redundant portion. A deepest portion of the dividing groove has an arc shape and the dividing groove includes a middle portion, and a width of the deepest portion is greater than a width of the groove inlet and a width of the middle portion is equal to or less than the width of the groove inlet.

    Abstract translation: 通过层叠多个陶瓷层而形成的多片阵列包括：在平面图中具有矩形形状并且包括空腔的多个布线板部分以矩阵布置的产品区域; 沿着产品区域的周边定位的冗余部分; 以及沿着布线板部分之间的边界和布线板部分和冗余部分之间的边界形成在前表面和/或后表面上的划分凹槽。 分隔槽的最深部分具有弧形，分隔槽包括中间部分，并且最深部分的宽度大于沟槽入口的宽度，并且中间部分的宽度等于或小于 槽入口宽度。

    Interconnect substrate, method of manufacturing interconnect substrate and semiconductor device
    34.
    发明授权
    Interconnect substrate, method of manufacturing interconnect substrate and semiconductor device 有权
    互连基板，制造互连基板和半导体器件的方法

    公开(公告)号：US08367939B2

    公开(公告)日：2013-02-05

    申请号：US12654017

    申请日：2009-12-08

    Applicant: Kiminori Ishido

    Inventor： Kiminori Ishido

    IPC: H05K1/16

    CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/099 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124 ,  H01L2224/0401

    Abstract: Embodiments of the invention provide an interconnect substrate capable of improving the connection reliability and yield of a semiconductor device, a method of manufacturing the interconnect substrate, and a semiconductor device using the interconnect substrate. An interconnect substrate according to an embodiment of the invention includes: a substrate; an electrode pad formed over the substrate; an insulating film (solder resist film) formed over the substrate; an opening formed in the insulating film, in which the upper surface of the electrode pad is exposed on the bottom surface of the opening and a metal film formed over the upper surface of the electrode pad and side surface of the insulating film in the opening. At least a portion of the edge of an upper surface of the metal film is higher than the other portions of the upper surface of the metal film.

    Abstract translation: 本发明的实施例提供了能够提高半导体器件的连接可靠性和产量的互连基板，制造互连基板的方法以及使用该互连基板的半导体器件。 根据本发明实施例的互连衬底包括：衬底; 形成在所述基板上的电极焊盘; 形成在基板上的绝缘膜（阻焊膜） 形成在绝缘膜上的开口，其中电极焊盘的上表面暴露在开口的底表面上，金属膜形成在电极焊盘的上表面和开口中的绝缘膜的侧表面上。 金属膜的上表面的边缘的至少一部分高于金属膜的上表面的其它部分。

    Cost-reducing and process-simplifying wiring board and manufacturing method thereof
    37.
    发明申请
    Cost-reducing and process-simplifying wiring board and manufacturing method thereof 失效
    降低成本和加工简化的布线板及其制造方法

    公开(公告)号：US20040266060A1

    公开(公告)日：2004-12-30

    申请号：US10859639

    申请日：2004-06-03

    Inventor： Shigetsugu Muramatsu ,  Tohru Hizume

    IPC: H01L021/00

    CPC classification number: H05K3/4644 ,  H05K3/005 ,  H05K3/421 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0108 ,  H05K2203/1189

    Abstract: A wiring board is disclosed that includes a first insulating layer, a conductor which is formed on a surface of the first insulating layer, and a second insulating layer which is formed on surfaces of the first insulating layer and of the conductor. The wiring board is provided with a semispherical-shaped or conical-shaped hole-forming portion which penetrates through the second insulating layer into the conductor.

    Abstract translation: 公开了一种布线板，其包括第一绝缘层，形成在第一绝缘层的表面上的导体和形成在第一绝缘层和导体的表面上的第二绝缘层。 布线板设置有半球形或圆锥形的孔形成部分，其穿过第二绝缘层进入导体。

    Method of manufacturing a printed wiring board
    39.
    发明申请
    Method of manufacturing a printed wiring board 有权
    制造印刷电路板的方法

    公开(公告)号：US20040052932A1

    公开(公告)日：2004-03-18

    申请号：US10643919

    申请日：2003-08-20

    Inventor： Yoshitaro Yazaki ,  Yoshihiko Shiraishi ,  Koji Kondo ,  Toshikazu Harada ,  Tomohiro Yokochi

    IPC: B05D005/12

    CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T428/24917

    Abstract: A heated and pressed printed wiring board is made by filling via holes formed in layers of insulating film of the wiring board with an interlayer conducting material. The insulating film is stacked with conductor patterns, and each conductor pattern closes a via hole. The interlayer conducting material forms a solid conducting material in the via holes after a heating a pressing procedure. The solid conducting material includes two types of conducting materials. The first type of conducting material includes a metal, and the second type of conductive material includes an alloy formed by the metal and conductor metal of the conductor patterns. The conductor patterns are electrically connected reliably without relying on mere mechanical contact.

    Abstract translation: 通过用层间导电材料填充形成在布线板的绝缘膜层上的孔，制成加压印刷线路板。 绝缘膜与导体图案堆叠，并且每个导体图案封闭通孔。 夹层导电材料在加压压制程序后在通孔中形成固体导电材料。 固体导电材料包括两种类型的导电材料。 第一类导电材料包括金属，第二类导电材料包括由导体图案的金属和导体金属形成的合金。 导体图形可靠地电连接，而不依赖于机械接触。

    Multilayer printed wiring board and method for manufacturing same
    40.
    发明申请
    Multilayer printed wiring board and method for manufacturing same 失效
    多层印刷电路板及其制造方法

    公开(公告)号：US20030188888A1

    公开(公告)日：2003-10-09

    申请号：US09808086

    申请日：2001-03-13

    Inventor： Hirokazu Yoshioka ,  Norio Yoshida ,  Kenichiro Tanaka

    IPC: H05K001/11 ,  H05K003/02

    CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

    Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 nullm in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

    Abstract translation: 多层印刷电路板形成有多个导体层，绝缘层整体层叠在一起，绝缘层中设置的非穿透通孔由导体层露出的底部，设置在通孔内部的镀层， 所述导体层之间的电连接，所述通孔形成为在通孔的内周到底面的连续区域的半径在20至100μm的范围内的轴向剖视图中的凹曲面的通孔，由此 在电镀镀层时发生的等电势面沿着连续区域弯曲，以统一电流密度，以使电镀层在厚​​度上均匀，而不会在连续区域变薄。

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