公开(公告)号：US20050097583A1

公开(公告)日：2005-05-05

申请号：US10973422

申请日：2004-10-27

Applicant: Yoshihiro Okumura

Inventor： Yoshihiro Okumura

IPC: G11B25/04 ,  G11B25/10 ,  G11B33/02 ,  G11B33/06 ,  G11B33/12 ,  H01B7/08 ,  H01B7/36 ,  H05K1/00 ,  G11B15/04 ,  G11B19/04

CPC classification number: G11B33/126 ,  G11B25/10 ,  G11B33/02 ,  G11B33/128 ,  H05K1/028 ,  H05K2201/055 ,  H05K2201/09936

Abstract: In a complex electronic device, in which device units are arranged so as to have substantially the same height of medium loading spaces, in connecting a circuit board for operation button control and each operation unit by use of FFCs, wiring in a limited space is possible even when the FFCs are bent or folded, without exerting an adverse effect on the arrangement of other parts. There is provided a complex electronic device in which in order to transmit operation signals of operation buttons of an optical disk recording/reading unit to an operation control circuit on a control circuit board of the unit, a connector (A) is arranged between the optical disk recording/reading unit and the control circuit board disposed below the optical disk recording/reading unit and on a side facing the front of devices on the control circuit board, and the connector (A) on the control circuit board and a connector (B) on the circuit board for operation button control are connected by a flexible flat cable that is bent or folded in a Z-shaped form by mountain folding and valley folding.

Abstract translation: 在复杂的电子设备中，其中设备单元布置成具有基本上相同的介质加载空间的高度，在通过使用FFC连接用于操作按钮控制的电路板和每个操作单元时，可以在有限的空间中布线 即使FFC弯曲或折叠，也不会对其他部件的布置产生不利影响。 提供了一种复杂的电子设备，其中为了将光盘记录/读取单元的操作按钮的操作信号发送到单元的控制电路板上的操作控制电路，连接器（A）设置在光学 光盘记录/读取单元和设置在光盘记录/读取单元下方以及面向控制电路板上的设备前面的一侧的控制电路板以及控制电路板上的连接器（A）和连接器（B ）用于操作按钮控制的电路板通过弯曲或折叠成Z形的柔性扁平电缆连接，通过山折叠和谷底折叠。

公开(公告)号：US20050046573A1

公开(公告)日：2005-03-03

申请号：US10485863

申请日：2002-04-30

Applicant: Francisco Velasco ,  Manfred Rietzler

Inventor： Francisco Velasco ,  Manfred Rietzler

IPC: B42D15/10 ,  G02B5/122 ,  G02B5/124 ,  G02B5/128 ,  G06K19/06 ,  G06K19/07 ,  G06K19/077 ,  G06K19/08 ,  G08B13/14 ,  G08B29/00 ,  G09F3/00 ,  G09F3/02 ,  H01Q1/38 ,  H05K1/00 ,  H05K3/06

CPC classification number: G06K19/0723 ,  G06K19/07 ,  G06K19/07718 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07758 ,  G06K19/0776 ,  G06K19/07771 ,  G06K19/07779 ,  G06K19/07783 ,  G06K2019/0629 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K1/0274 ,  H05K1/0393 ,  H05K3/067 ,  H05K2201/0133 ,  H05K2201/09781 ,  H05K2201/09936 ,  H05K2201/2054 ,  H05K2203/0143 ,  H05K2203/1545 ,  H01L2924/00

Abstract: A method for selectively removing metal from a metallized substrate (e.g., a metallized polymer film) and the formation of devices thereby are provided. Th method involves selectively exposing the metallized surface to a demetallizing (i.e., an oxidizing) chemical solution. The metallized layer can be selectively exposed to the demetallizing solution using a flexographic printing process wherein printing rollers are used to transfer the demetallizing solution to the metallized surface. An identification device including, for example, a holographic, retro-reflective, or other metallized material and a radio-frequency transponder are also provided. The radio-frequency transponder includes an RF chip and an antenna in electrical communication with the chip. The identification device including the holographic image allows both electronic identification through the reading or identification data stored in the chip and optical identification via the holographic image.

Abstract translation: 提供了从金属化基板（例如，金属化聚合物膜）选择性地去除金属并由此形成器件的方法。 Th方法包括将金属化表面选择性地暴露于脱金属（即氧化）化学溶液。 金属化层可以使用柔性版印刷方法选择性地暴露于脱金属溶液，其中使用印刷辊将去金属化溶液转移到金属化表面。 还提供了包括例如全息，回射或其它金属化材料和射频转发器的识别装置。 射频转发器包括RF芯片和与芯片电连通的天线。 包括全息图像的识别装置允许通过存储在芯片中的读取或识别数据进行电子识别，并通过全息图像进行光学识别。

公开(公告)号：US06855626B2

公开(公告)日：2005-02-15

申请号：US10637552

申请日：2003-08-11

Applicant: Yukio Sato ,  Akihiro Oku ,  Masayoshi Aoki

Inventor： Yukio Sato ,  Akihiro Oku ,  Masayoshi Aoki

IPC: H01L21/66 ,  H01L23/544 ,  H05K1/02 ,  H05K3/00 ,  H05K3/24 ,  H01L21/4763

CPC classification number: H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0266 ,  H05K3/0052 ,  H05K3/242 ,  H05K2201/09227 ,  H05K2201/09936 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/01004

Abstract: A method for producing a wiring board for a semiconductor package having a base substrate with first and second surfaces; a wiring layer including wiring patterns formed on at least one of the first and second surfaces; a plurality of semiconductor element mounting areas formed on the surface of the base substrate on which the wiring layer is formed; and individual patterns as position information formed for the respective semiconductor element mounting areas, the individual patterns having a different shape for each of the respective semiconductor element mounting areas. The individual patterns as position information are formed on peripheral regions of the respective semiconductor element mounting areas.

Abstract translation: 一种半导体封装用配线基板的制造方法，具有：具有第一表面和第二表面的基底基板; 布线层，其包括形成在所述第一表面和所述第二表面中的至少一个上的布线图案; 多个半导体元件安装区域，形成在其上形成有布线层的基底基板的表面上; 以及作为为各个半导体元件安装区域形成的位置信息的各个图案，各个图案对于各个半导体元件安装区域具有不同的形状。 作为位置信息的各个图案形成在各个半导体元件安装区域的周边区域上。

公开(公告)号：US06705509B2

公开(公告)日：2004-03-16

申请号：US10103572

申请日：2002-03-22

Applicant: Sakari Tada ,  Eietsu Hasegawa

Inventor： Sakari Tada ,  Eietsu Hasegawa

IPC: B23K3102

CPC classification number: B23K1/018 ,  B23K2101/42 ,  H05K1/0266 ,  H05K3/3463 ,  H05K2201/09936 ,  H05K2203/178 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49757 ,  Y10T29/49787 ,  Y10T29/49821

Abstract: Discarded printed circuit boards are sorted according to the alloying elements in solder used on the printed circuit boards. After sorting, the printed circuit boards are heated to melt the solder, and the molten solder is collected.

Abstract translation: 根据印刷电路板上使用的焊料中的合金元素分选抛光印刷电路板。 分选后，印刷电路板被加热以熔化焊料，并且收集熔融的焊料。

公开(公告)号：US20030058625A1

公开(公告)日：2003-03-27

申请号：US10253545

申请日：2002-09-25

Inventor： Chih-Ching Chen ,  Yi-Jing Leu

IPC: H05K001/00

CPC classification number: B41J2/17559 ,  B41J2/1753 ,  B41J2/17546 ,  H05K1/0266 ,  H05K1/0269 ,  H05K1/0393 ,  H05K3/28 ,  H05K2201/09936 ,  H05K2203/0514 ,  H05K2203/161 ,  Y10S29/016 ,  Y10S428/901 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/31507 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31786

Abstract: The invention discloses an identifiable flexible printed circuit board (PCB) and a method of fabricating the same. The identifiable flexible PCB includes a flexible substrate, a conductive layer, and a printing ink layer. First, the conductive layer is formed over a surface of the flexible substrate. Second, the printing ink layer is formed on the surface of the flexible substrate by coating, exposing, and developing to uncover parts of the conductive layer. Also, at least one identifiable area is formed on the printing ink layer and one can easily and correctly identify the cartridge with the flexible PCB.

Abstract translation: 本发明公开了一种可识别的柔性印刷电路板（PCB）及其制造方法。 可识别的柔性PCB包括柔性基板，导电层和印刷油墨层。 首先，在柔性基板的表面上形成导电层。 其次，通过涂布，曝光和显影以形成导电层的部分，在柔性基板的表面上形成印刷油墨层。 此外，在印刷油墨层上形成至少一个可识别的区域，并且可以容易且正确地识别带柔性PCB的盒。

公开(公告)号：US20030001256A1

公开(公告)日：2003-01-02

申请号：US10179981

申请日：2002-06-26

Applicant: Shinko Electric Industries Co., LTD.

Inventor： Yukio Sato ,  Akihiro Oku ,  Masayoshi Aoki

IPC: H01L023/34

CPC classification number: H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0266 ,  H05K3/0052 ,  H05K3/242 ,  H05K2201/09227 ,  H05K2201/09936 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/01004

Abstract: A wiring board for a semiconductor package comprises a base substrate having first and second surfaces; a wiring layer consisting of necessary wiring patterns formed on at least one of the first and second surfaces; a plurality of semiconductor element mounting areas formed on the surface of the base substrate on which the wiring layer is formed; and individual patterns as position information provided for the respective semiconductor element mounting areas, the individual patterns having a particular shape for the respective semiconductor element mounting area. The individual patterns as position information are formed on peripheral regions of the respective semiconductor element mounting areas.

Abstract translation: 一种用于半导体封装的布线板包括具有第一和第二表面的基底基板; 由形成在所述第一表面和所述第二表面中的至少一个上的必要布线图形构成的布线层; 多个半导体元件安装区域，形成在其上形成有布线层的基底基板的表面上; 以及作为为各个半导体元件安装区域提供的位置信息的各个图案，各个图案具有用于各个半导体元件安装区域的特定形状。 作为位置信息的各个图案形成在各个半导体元件安装区域的周边区域上。

公开(公告)号：US20010048592A1

公开(公告)日：2001-12-06

申请号：US09803024

申请日：2001-03-12

Applicant: Kabushiki Kaisha Toshiba.

Inventor： Ryoji Ninomiya

IPC: H05K007/02

CPC classification number: H05K1/0246 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0269 ,  H05K1/112 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09909 ,  H05K2201/09936 ,  H05K2201/10022 ,  H05K2201/10636 ,  H05K2203/161 ,  Y02P70/611

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

Abstract translation: 在地层上形成绝缘层。 绝缘层包括用于形成布线层的第一和第二区域。 形成在第二区域上的布线层的阻抗低于形成在第一区域上的布线层的阻抗。 在绝缘层的第一区域上的布线层上形成信号线图形。 在绝缘层的第二区域上的布线层上形成电源平面，以便通过连接到信号线图形的终端电阻向信号线图案供电。

公开(公告)号：US06289306B1

公开(公告)日：2001-09-11

申请号：US08966375

申请日：1997-11-07

Applicant: Renatus J. Van Der Vleuten ,  Alphons A. M. L. Bruekers ,  Arnoldus W. J. Oomen

Inventor： Renatus J. Van Der Vleuten ,  Alphons A. M. L. Bruekers ,  Arnoldus W. J. Oomen

IPC: G10L302

CPC classification number: G11B20/10 ,  G11B20/00007 ,  G11B20/10037 ,  G11B20/10527 ,  G11B2020/00065 ,  H03M7/3002 ,  H05K1/0266 ,  H05K3/381 ,  H05K2201/09936 ,  H05K2203/161

Abstract: A data processing apparatus includes an input terminal for receiving an audio signal, a 1-bit A/D converter for A/D converting the audio signal so as to obtain a bitstream signal, and a prediction unit for carrying out a prediction step on the bitstream signal so as to obtain a predicted bitstream signal. The data processing apparatus further includes a signal combination unit for combining the bitstream signal and the predicted bitstream signal so as to obtain a residue bitstream signal, and an output terminal for supplying the residual bitstream signal. A recording apparatus or a transmitter apparatus can use the data processing apparatus.

Abstract translation: 一种数据处理装置，包括用于接收音频信号的输入端子，用于对音频信号进行A / D转换的1位A / D转换器，以获得位流信号;以及预测单元，用于对 以获得预测比特流信号。 数据处理装置还包括信号组合单元，用于组合比特流信号和预测比特流信号，以获得残留比特流信号;以及输出端，用于提供残留比特流信号。 记录装置或发送装置可以使用数据处理装置。

公开(公告)号：US5266748A

公开(公告)日：1993-11-30

申请号：US670320

申请日：1991-03-15

Applicant: Shin Kawakami ,  Hirotaka Okonogi ,  Katsutomo Nikaido ,  Junichi Ichikawa ,  Yoshio Nishiyama

Inventor： Shin Kawakami ,  Hirotaka Okonogi ,  Katsutomo Nikaido ,  Junichi Ichikawa ,  Yoshio Nishiyama

IPC: H05K3/28 ,  H05K1/02 ,  H05K3/00 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/0094 ,  H05K1/0218 ,  H05K3/3452 ,  H01L2924/15151 ,  H05K1/0266 ,  H05K2201/0715 ,  H05K2201/09072 ,  H05K2201/09936 ,  H05K2203/0577 ,  H05K2203/1394 ,  H05K3/42 ,  H05K3/4644

Abstract: A printed wiring board includes a substrate having an electrically conductive pattern disposed on at least one side of the substrate. An electrically conductive through-hole is formed in the substrate. At least one of a solder resist film and an electromagnetic shielding layer undercoat film are disposed over the conductive pattern but do not cover the electrically conductive through-hole. An ink layer is formed over at least one end of the electrically conductive through-hole. A method of manufacturing the printed wiring board embodied by the invention comprises providing a substrate having an electrically conductive through-hole. A conductive pattern is formed on at least one side of the substrate. At least one of a solder resist film and an electromagnetic shielding layer undercoat film are formed over the conductive pattern but not over the electrically conductive through-hole. An ink layer is formed over at least one end of the electrically conductive through-hole. The ink layer may be formed simultaneously with the printing of symbols of electronic parts to be mounted on the printed wiring board.

Abstract translation: 印刷布线板包括具有设置在基板的至少一侧上的导电图案的基板。 在基板上形成导电孔。 阻焊膜和电磁屏蔽层底涂层中的至少一个设置在导电图案之上，但不覆盖导电通孔。 在导电通孔的至少一端形成油墨层。 本发明实施的制造印刷电路板的方法包括提供具有导电通孔的基板。 在衬底的至少一侧上形成导电图案。 在导电图案上形成阻焊膜和电磁屏蔽层底涂膜中的至少一个，但不在导电通孔上。 在导电通孔的至少一端形成油墨层。 油墨层可以与印刷要印刷的电路板的电子部件的符号同时形成。

公开(公告)号：US3880610A

公开(公告)日：1975-04-29

申请号：US42485373

申请日：1973-12-14

Applicant: US TRANSPORT

Inventor： LONG LENNART E

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/22

CPC classification number: H05K1/029 ,  H05K3/0005 ,  H05K3/222 ,  H05K2201/09354 ,  H05K2201/09936 ,  H05K2201/10287 ,  H05K2203/173 ,  Y10T29/49155

Abstract: A method of fabricating universal circuit boards which can be utilized in making up the most common circuit elements, such as amplifiers and the like, to be in turn combined to make up any number of customed design electronic devices. The universal printed circuit board disclosed has numerous paths which can be alternately utilized to provide a combination of many possible circuits. This board can then be used with other similarly designed boards to fabricate complete custom-designed electronic equipment.

Abstract translation: 一种制造通用电路板的方法，其可用于构成最常见的电路元件，例如放大器等，从而组合以组成任何数量的定制设计电子设备。 所公开的通用印刷电路板具有许多路径，其可以交替地用于提供许多可能的电路的组合。 然后，该板可以与其他类似设计的板一起使用，以制造完整的定制设计的电子设备。