公开(公告)号：US07989707B2

公开(公告)日：2011-08-02

申请号：US11815580

申请日：2006-12-12

Applicant: Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

Inventor： Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

IPC: H05K1/16

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract translation: 公开了一种制造芯片嵌入式基板的方法。 该方法包括将半导体芯片安装在其上形成有第一布线的第一基板上的第一步骤; 以及将第一基板与形成有第二布线的第二基板接合的第二步骤。 在第二步骤中，将半导体芯片封装在第一基板和第二基板之间，并且在第一布线和第二布线之间形成电连接，以形成连接到半导体芯片的多层布线。

公开(公告)号：US20240290687A1

公开(公告)日：2024-08-29

申请号：US18114576

申请日：2023-02-27

Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.

Inventor： Feng Zhou ,  Tianzhu Fan ,  Yanghe Liu

IPC: H01L23/427 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/427 ,  H01L24/32 ,  H05K1/0203 ,  H05K1/185 ,  H01L2224/32221 ,  H01L2924/1011 ,  H05K2201/064 ,  H05K2201/10007

Abstract: A power device embedded printed circuit board (PCB) assembly includes a cold plate, a multi-layer PCB with at least one power device embedded therein bonded to and in thermal communication with the cold plate, and a chemical vapor deposition (CVD) dielectric layer disposed between the cold plate and the multi-layer PCB. The CVD dielectric layer can be applied to the cold plate and a bonding layer can be sandwiched between the CVD dielectric layer and the multi-layer PCB with at least one power device assembly embedded therein. In the alternative, CVD dielectric layer can be applied top the multi-layer PCB with at least one power device assembly embedded therein and bonding layer can be sandwiched between the CVD dielectric layer and the cold plate.

公开(公告)号：US20240244760A1

公开(公告)日：2024-07-18

申请号：US18559526

申请日：2022-05-12

Applicant: ams-OSRAM International GmbH

Inventor： Thomas Schwarz

IPC: H05K3/12 ,  H05K1/18 ,  H05K3/40 ,  H05K13/00

CPC classification number: H05K3/1275 ,  H05K1/181 ,  H05K3/4007 ,  H05K13/0015 ,  H05K2201/10007

Abstract: In an embodiment a carrier structure includes at least one conductor structure configured for electrically contacting electrical components, wherein the conductor structure includes a plurality of conductor bodies, wherein at least some of the conductor bodies are in direct contact with electrically conductive first connectors, and wherein the conductor structure includes the conductor bodies and the first connectors.

公开(公告)号：US12014868B2

公开(公告)日：2024-06-18

申请号：US17165933

申请日：2021-02-02

Applicant: CYNTEC CO., LTD.

Inventor： Yi-Cheng Lin

IPC: H05K1/09 ,  H01F27/255 ,  H01F41/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H05K3/40 ,  H01F1/22

CPC classification number: H01F41/0233 ,  H01F27/255 ,  H01F41/0246 ,  H05K1/09 ,  H05K1/111 ,  H05K1/18 ,  H05K3/341 ,  H05K3/40 ,  H01F1/22 ,  H05K2201/09009 ,  H05K2201/10007

Abstract: An electrode structure on a circuit board, the electrode structure comprising a metal structure disposed on and electrically connected to the circuit board, wherein the metal structure and a surface of the circuit board forms a space therebetween, wherein at least one first electrical component is disposed in the space and an outer surface of the metal structure forms an electrode for electrically connecting with an external component.

公开(公告)号：US09999131B2

公开(公告)日：2018-06-12

申请号：US14991608

申请日：2016-01-08

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyung-Hwan Ko ,  Young-Gwan Ko ,  Jae-Ean Lee ,  Jee-Soo Mok ,  Yong-Ho Baek

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H01L23/28 ,  H05K3/28 ,  H05K1/16

CPC classification number: H05K1/183 ,  H01L24/14 ,  H01L24/17 ,  H01L24/49 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/17 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73257 ,  H01L2924/00014 ,  H05K1/115 ,  H05K1/162 ,  H05K1/182 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/09381 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10022 ,  H05K2201/1003 ,  H01L2224/45099

Abstract: A printed circuit board including an electronic component and a method of producing the same are provided. The printed circuit board includes a multilayered substrate including an insulation layer and an inner circuit layer laminated therein, a cavity disposed in the multilayered substrate, a via disposed in the insulation layer and configured to electrically connect the inner circuit layer with another inner circuit layer, a first electronic component inserted in the cavity, and a bump pad disposed on a surface of the cavity facing the first electronic component, and the bump pad is formed by having the insulation layer and the via exposed to a lateral side of the cavity.

公开(公告)号：US20170365559A1

公开(公告)日：2017-12-21

申请号：US15676288

申请日：2017-08-14

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Takaharu YAMANO ,  Hajime IIZUKA ,  Hideaki SAKAGUCHI ,  Toshio KOBAYASHI ,  Tadashi ARAI ,  Tsuyoshi KOBAYASHI ,  Tetsuya KOYAMA ,  Kiyoaki IIDA ,  Tomoaki MASHIMA ,  Koichi TANAKA ,  Yuji KUNIMOTO ,  Takashi YANAGISAWA

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/16 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H05K1/18 ,  H01L23/552 ,  H01L23/498 ,  H05K3/46 ,  H05K3/20

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

公开(公告)号：US09768122B2

公开(公告)日：2017-09-19

申请号：US15241482

申请日：2016-08-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

IPC: H05K1/16 ,  H01L23/538 ,  H01L21/683 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H05K3/20 ,  H05K3/46

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

公开(公告)号：US20160219712A1

公开(公告)日：2016-07-28

申请号：US14991608

申请日：2016-01-08

Applicant: Samsung-Electro-Mechanics Co., Ltd.

Inventor： Kyung-Hwan Ko ,  Young-Gwan Ko ,  Jae-Ean Lee ,  Jee-Soo Mok ,  Yong-Ho Baek

IPC: H05K1/18 ,  H05K3/46 ,  H05K3/32 ,  H05K1/11 ,  H05K3/30

CPC classification number: H05K1/183 ,  H01L24/14 ,  H01L24/17 ,  H01L24/49 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/17 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73257 ,  H01L2924/00014 ,  H05K1/115 ,  H05K1/162 ,  H05K1/182 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/09381 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10022 ,  H05K2201/1003 ,  H01L2224/45099

Abstract: A printed circuit board including an electronic component and a method of producing the same are provided. The printed circuit board includes a multilayered substrate including an insulation layer and an inner circuit layer laminated therein, a cavity disposed in the multilayered substrate, a via disposed in the insulation layer and configured to electrically connect the inner circuit layer with another inner circuit layer, a first electronic component inserted in the cavity, and a bump pad disposed on a surface of the cavity facing the first electronic component, and the bump pad is formed by having the insulation layer and the via exposed to a lateral side of the cavity.

Abstract translation: 提供一种包括电子部件的印刷电路板及其制造方法。 印刷电路板包括：多层基板，包括层压在其中的绝缘层和内部电路层;设置在所述多层基板中的空腔;布置在所述绝缘层中并且构造成将所述内部电路层与另一内部电路层电连接的通孔， 插入该空腔中的第一电子部件和设置在面向第一电子部件的空腔的表面上的凸块焊盘，并且通过使绝缘层和通孔暴露于空腔的侧面而形成凸块焊盘。

公开(公告)号：US20150181740A1

公开(公告)日：2015-06-25

申请号：US14640873

申请日：2015-03-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Seiji TOKII ,  Manabu TASAKI

IPC: H05K7/02 ,  H05K13/04

CPC classification number: H05K7/02 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/181 ,  H05K1/182 ,  H05K3/284 ,  H05K3/301 ,  H05K3/3447 ,  H05K13/04 ,  H05K2201/10007 ,  H05K2201/10159 ,  H05K2201/10583 ,  H05K2201/10674

Abstract: A mounting structure for an electronic component and a method for mounting the electronic component are provided with a sufficient reinforcing effect for the relatively tall electronic component raised from a substrate. The mounting structure and the mounting method can easily respond to a change of the shape of the electronic component. In a mounting structure 1, a substrate 2 and an electronic component 4 raised on the substrate 2 are joined with bonding metal 3 and a reinforcing resin body 5 is bonded to the substrate 2 and the electronic component 4. The reinforcing resin body 5 includes a plurality of reinforcing resin layers 5a. The reinforcing resin layers 5a constituting the reinforcing resin body 5 are stacked in the height direction of the raised electronic component 4 along a side 4a of the electronic component 4 so as to be raised from the substrate 2.

Abstract translation: 电子部件的安装结构和用于安装电子部件的方法为从衬底升起的较高的电子部件提供充分的增强效果。 安装结构和安装方法可以容易地响应于电子部件的形状的变化。 在安装结构体1中，将基板2和在基板2上升起的电子部件4与接合金属3接合，并且将强化树脂体5接合到基板2和电子部件4.增强树脂体5包括 多个增强树脂层5a。 构成加强树脂体5的增强树脂层5a沿着电子部件4的侧面4a沿升高的电子部件4的高度方向堆叠，从基板2升起。

公开(公告)号：US08793868B2

公开(公告)日：2014-08-05

申请号：US13167203

申请日：2011-06-23

Applicant: Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

Inventor： Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

IPC: H05K3/30

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract translation: 公开了一种制造芯片嵌入式基板的方法。 该方法包括将半导体芯片安装在其上形成有第一布线的第一基板上的第一步骤; 以及将第一基板与形成有第二布线的第二基板接合的第二步骤。 在第二步骤中，将半导体芯片封装在第一基板和第二基板之间，并且在第一布线和第二布线之间形成电连接，以形成连接到半导体芯片的多层布线。