公开(公告)号：US5801601A

公开(公告)日：1998-09-01

申请号：US789749

申请日：1997-01-27

Applicant: Christopher R. Gayle

Inventor： Christopher R. Gayle

IPC: H01P7/00 ,  H05K1/02 ,  H05K3/22 ,  H01P1/18

CPC classification number: H05K1/0248 ,  H01P7/00 ,  H05K2201/0715 ,  H05K2201/09263 ,  H05K2201/09336 ,  H05K2201/10174 ,  H05K2201/10363 ,  H05K3/222

Abstract: A printed circuit board with a microstrip radio frequency delay line deposited thereon. In addition, a plurality of delay line segments are deposited on the board in close proximity to one end of the delay line. To achieve an overall desired delay length, one of the delay line segments is selected and serially inserted in circuit with the delay line by populating a surface mount circuit element between terminals at the ends of the delay line and the selected delay line segment.

Abstract translation: 具有沉积在其上的微带射频延迟线的印刷电路板。 此外，多个延迟线段沉积在板上，紧邻延迟线的一端。 为了实现总体期望的延迟长度，通过在延迟线的端部和所选择的延迟线段的端子之间填充表面安装电路元件，选择一个延迟线段并且与延迟线串联插入到电路中。

公开(公告)号：US5416274A

公开(公告)日：1995-05-16

申请号：US156915

申请日：1993-11-24

Applicant: Kiyohiko Ushiyama ,  Shizunori Mitsuma

Inventor： Kiyohiko Ushiyama ,  Shizunori Mitsuma

IPC: H05K1/11 ,  H05K3/22 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/222 ,  H05K3/4685 ,  H05K2201/10287 ,  H05K2201/10363

Abstract: An object of this invention is to provide a circuit board low in manufacturing cost in which aimed circuit patterns having a circuit gap therebetween can be short-circuited substantially irrespective of the length of the circuit gap while being insulated from other circuit patterns which are laid in the circuit gap. In a circuit board on which a plurality of circuit patterns are arranged, a selected one of circuit patterns is cut to have a circuit gap where the selected circuit pattern is laid across the remaining circuit patterns, in such a manner that the circuit gap divides the selected circuit patterns into two parts, a conductor formed by cutting a wire to the length of the circuit gap bridges the circuit gap, to short-circuit the two parts thereby to complete the selected circuit pattern, the conductor being insulated from the remaining circuit patterns laid across the circuit gap.

Abstract translation: 本发明的目的是提供一种制造成本低的电路板，其中具有电路间隙的目标电路图案可以与电路间隙的长度基本上短路，同时与放置在其中的其它电路图案绝缘 电路间隙。 在其上布置多个电路图形的电路板中，选择的一个电路图案被切割成具有电路间隙，其中所选择的电路图案跨越剩余的电路图案，使得电路间隙将 所选择的电路图案分成两部分，通过将线切割到电路间隙的长度而形成的导体桥接电路间隙，使两部分短路，从而完成所选择的电路图案，导体与剩余电路图案绝缘 跨越电路间隙。

公开(公告)号：US5047895A

公开(公告)日：1991-09-10

申请号：US293411

申请日：1989-01-04

Applicant: Takahide Sasaki

Inventor： Takahide Sasaki

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K3/4685 ,  H05K1/118 ,  H01R12/59 ,  H05K2201/052 ,  H05K2201/09081 ,  H05K2201/10363 ,  H05K3/361

Abstract: A flexible printed circuit board, which has a plurality of signal lines and allows end portions of the signal lines to be electrically connected to another member, is arranged such that an end portion of at least one signal line is made to detour around an end portion of another signal line so as to be introduced into a portion for electrical connection.

Abstract translation: 具有多个信号线并且允许信号线的端部电连接到另一个部件的柔性印刷电路板被布置成使得至少一条信号线的端部围绕端部部分迂回 的另一个信号线，以便被引入用于电连接的部分。

公开(公告)号：US4869671A

公开(公告)日：1989-09-26

申请号：US158531

申请日：1988-02-22

Applicant: Allan H. Pressley ,  David L. Zick

Inventor： Allan H. Pressley ,  David L. Zick

IPC: H01R12/00 ,  H05K3/22 ,  H05K3/30

CPC classification number: H01R12/57 ,  H05K3/222 ,  H05K2201/10363 ,  H05K3/305

Abstract: An electrical conductor fashioned from an electrically conductive material such as copper has a body portion and a pair of laterally extending legs. The body portion and the legs cooperate to define a recess which is substantially filled with an insulating material. That insulating material has a surface recessed from the ends of the legs toward the body portion that, along with the surface of the printed circuit board defines a gap which is suitably sized to receive an epoxy adhesive for temporarily attaching the electrical conductor to the printed circuit board.

Abstract translation: 由诸如铜的导电材料形成的电导体具有主体部分和一对横向延伸的支腿。 身体部分和腿部协作以限定基本上填充有绝缘材料的凹部。 该绝缘材料具有从腿的端部朝向主体部分凹陷的表面，其与印刷电路板的表面一起限定了适当尺寸以接收环氧粘合剂的间隙，用于将电导体临时附接到印刷电路 板。

公开(公告)号：US4040121A

公开(公告)日：1977-08-02

申请号：US581223

申请日：1975-05-27

Applicant: Reed H. Grundy

Inventor： Reed H. Grundy

IPC: H05K1/02 ,  H05K3/22 ,  H05K3/30 ,  H05K3/34 ,  H05K3/40 ,  H05K5/00

CPC classification number: H05K3/3447 ,  H05K3/308 ,  H05K2201/09418 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10363 ,  H05K2201/10651 ,  H05K2201/10939 ,  H05K3/222 ,  H05K3/4046

Abstract: The external lead from a critical circuit element in a circuit component of a larger apparatus is connected to a first terminal or connector pad on a printed circuit board and at a more distant point on the lead to a second connector pad. The connection to the next element of that component is made from the second pad. Any component output to the next circuit component is connected to the first pad. Thus, any high resistance in a poor solder joint appears on the safe side of the first pad connections, that is, in the circuit connections to the next element or in the output circuit.

公开(公告)号：US3729816A

公开(公告)日：1973-05-01

申请号：US3729816D

申请日：1971-12-02

Applicant: WESTERN ELECTRIC CO

Inventor： BURNS J

IPC: H05K3/22 ,  H05K13/00 ,  B01J17/00

CPC classification number: H05K3/222 ,  H05K13/003 ,  H05K2201/1028 ,  H05K2201/10363 ,  H05K2203/173 ,  Y10T29/49004

Abstract: An electrical circuit is formed by a process which permits the electrical testing of portions of the circuit during the circuit forming process. One or more temporary crossover members are formed, which may interconnect certain circuit paths, while spanning and not contacting other paths eventually to be interconnected into the circuit. The temporary crossover members are preferably formed, along with any other crossover members and/or electrical components desired, on a carrier member and then transferred onto a dielectric substrate carrying the circuit paths. Electrical testing of the incomplete circuit follows. The circuit is thereafter completed with deformation of the temporary crossover members into electrical contact with the spanned circuit paths and bonding the deformed crossover portions to the spanned paths.

Abstract translation: 通过在电路形成过程中允许对电路的部分进行电测试的过程形成电路。 形成一个或多个临时交叉构件，其可以互连某些电路路径，同时跨越并且不接触最终互连到电路中的其他路径。 临时交叉构件优选与载体构件上所需的任何其它交叉构件和/或电组件一起形成，然后转移到承载电路路径的电介质衬底上。 不完全电路的电气测试如下。 然后，电路随着临时交叉构件的变形与跨接的电路路径电接触并将变形的交叉部分结合到跨越路径而完成。

公开(公告)号：US3486160A

公开(公告)日：1969-12-23

申请号：US3486160D

申请日：1968-05-29

Applicant: SUSQUEHANNA CORP

Inventor： WALLACE JACOB L JR

IPC: H01R4/46 ,  H01R12/70 ,  H05K1/00 ,  H05K3/22 ,  H05K1/02

CPC classification number: H05K3/222 ,  H01R4/46 ,  H01R12/7076 ,  H05K1/0289 ,  H05K1/029 ,  H05K2201/10053 ,  H05K2201/10363

公开(公告)号：US12132002B2

公开(公告)日：2024-10-29

申请号：US18139862

申请日：2023-04-26

Applicant: Intel Corporation

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L23/5381 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H05K1/185 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/81481 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/04953 ,  H01L2224/81487 ,  H01L2924/04941 ,  H01L2224/81466 ,  H01L2924/01074 ,  H01L2224/81463 ,  H01L2924/01072 ,  H01L2224/81479 ,  H01L2924/00014 ,  H01L2224/8147 ,  H01L2924/00014 ,  H01L2224/81472 ,  H01L2924/00014 ,  H01L2224/81484 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2224/81487 ,  H01L2924/0481 ,  H01L2924/01029 ,  H01L2224/81487 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2224/171 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20240349421A1

公开(公告)日：2024-10-17

申请号：US18415699

申请日：2024-01-18

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： CHIA-LUNG WANG ,  Min-Hung Huang

IPC: H05K1/02 ,  H01L23/538

CPC classification number: H05K1/0292 ,  H01L23/5382 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/10022 ,  H05K2201/10053 ,  H05K2201/10363

Abstract: A layout without bridge taps includes: a routing from a CPU to a first module through a first set of pads; a routing from a first set of bridge pads to a second module through a second set of pads and a second set of bridge pads; a routing from a third set of pads to a third module; and connectors. The connectors connect pads of the first set of pads to couple the CPU with the first module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the second set of bridge pads to couple the CPU with the second module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the third set of pads to couple the CPU with the third module.

公开(公告)号：US12117351B2

公开(公告)日：2024-10-15

申请号：US17326544

申请日：2021-05-21

Applicant: QUANTA COMPUTER INC.

Inventor： Hsiao-Tsu Ni ,  Ying-Che Chang ,  Chao-Nan Lin

IPC: G01K11/00 ,  H05K1/18 ,  H05K7/04

CPC classification number: G01K11/006 ,  H05K1/181 ,  H05K7/04 ,  H05K2201/10151 ,  H05K2201/10181 ,  H05K2201/10363

Abstract: A system includes a first printed circuit board (PCB), a temperature sensor, a switching circuit provided on the first PCB, and a controller. The temperature sensor is configured to measure temperature of at least an area of the first PCB. The controller is configured to trigger the switching circuit to turn off power to the first PCB, based at least in part on the temperature sensor detecting a temperature above a temperature threshold. The system is able to disrupt power much faster than conventional methods of power protection which may have a blind spot to certain areas of the first PCB, since these methods rely on power disruption when a maximum power is sensed.