公开(公告)号：US20030116860A1

公开(公告)日：2003-06-26

申请号：US10023723

申请日：2001-12-21

Inventor： Biju Chandran ,  Carlos A. Gonzalez

IPC: H01L023/48

CPC classification number: H01L24/81 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10992 ,  Y02P70/613 ,  H01L2924/00

Abstract: A low resistance package-to-die interconnect scheme for reduced die stresses includes a relatively low melting temperature and yield strength solder on the die and a relatively higher melting temperature and electrically conductive material such as copper on the substrate. A soldered joint connects the solder to the electrically conductive material to couple/connect the die and substrate to one another. The soldered joint is formed by heating the die and solder thereon to at least the melting temperature of the solder and thereafter contacting the molten solder with the conductive material on the substrate, which is at a substantially lower temperature for minimizing residual stress from soldering due to coefficient of thermal expansion mismatch between the substrate and die.

Abstract translation: 用于减小管芯应力的低电阻封装到管芯互连方案包括相对低的熔化温度和管芯上的屈服强度焊料以及相对较高的熔化温度和导电材料（例如基底上的铜）。 焊接接头将焊料连接到导电材料以将管芯和衬底彼此连接/连接。 钎焊接头是通过将模具加热至其上的至少熔化温度形成的，然后使熔融焊料与衬底上的导电材料接触，该导电材料处于基本上较低的温度，以使由于焊接造成的残余应力最小化 基板和模具之间的热膨胀系数不匹配。

公开(公告)号：US20030099767A1

公开(公告)日：2003-05-29

申请号：US10329265

申请日：2002-12-24

Inventor： Jen-Kuang Fang

IPC: B05D005/12

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01R4/024 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10977 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T29/49149 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2924/013

Abstract: A bumping process for chip scale packaging comprises: providing a chip, the chip having an active surface that has a plurality of bonding pads; sequentially forming an under bump metal (UBM) structure and a leaded bump thereon on each of the bonding pads, wherein the material of the leaded bumps is composed of tin and more than 85% of lead; forming a thermosetting plastic on the active surface that covers the leaded bumps; and grinding the surface of the thermosetting plastic to expose the leaded bumps.

公开(公告)号：US20030079909A1

公开(公告)日：2003-05-01

申请号：US10032908

申请日：2001-11-01

Inventor： Chinh Nguyen ,  Phu Hoang ,  Phan Hoang ,  Andy Le

IPC: H01L023/488

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/144 ,  H05K3/3421 ,  H05K3/3463 ,  H05K2201/0367 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10992 ,  H05K2203/043 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: In one embodiment of the invention, a stacking element includes a printed circuit board (PCB) and a plurality of solder bumps. The PCB has a top side and a bottom side. The top side is attached to first pins of a first device. The plurality of solder bumps are on the bottom side and attached to upper areas of second pins of a second device to provide electrical connections between the first pins and the second pins.

Abstract translation: 在本发明的一个实施例中，堆叠元件包括印刷电路板（PCB）和多个焊料凸块。 PCB具有顶侧和底侧。 顶侧连接到第一设备的第一个引脚。 多个焊料凸块位于底侧，并附接到第二器件的第二引脚的上部区域，以提供第一引脚和第二引脚之间的电连接。

公开(公告)号：US06547124B2

公开(公告)日：2003-04-15

申请号：US09881251

申请日：2001-06-14

Applicant: Tushar T. Shah ,  Andrew TS Pomerene ,  Keith K. Sturcken ,  Steven J. Wright

Inventor： Tushar T. Shah ,  Andrew TS Pomerene ,  Keith K. Sturcken ,  Steven J. Wright

IPC: B23K3512

CPC classification number: H01L24/12 ,  B23K35/0222 ,  B23K2101/40 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/10992 ,  H05K2203/0415 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of forming a plurality of micro column interconnection structures on a semiconductor includes providing a semiconductor layer. A photoresist layer is formed on the semiconductor layer. A plurality of cavities are etched in the photoresist layer. The plurality of cavities extend through the photoresist layer to the semiconductor layer. Solder is deposited in the plurality of cavities, thereby forming a plurality of micro columns of solder.

公开(公告)号：US06507121B2

公开(公告)日：2003-01-14

申请号：US09756086

申请日：2001-01-08

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L2348

CPC classification number: H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10992 ,  H05K2201/2036 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array. At least three solder balls coated with the base material having a high melting-temperature core are further provided in the periphery of the array. The carrier is arranged such that the active surface faces the first surface of the substrate to allow each solder ball correspond to the one of the pads, respectively.

公开(公告)号：US06504105B1

公开(公告)日：2003-01-07

申请号：US08640645

申请日：1996-05-01

Applicant: John Acocella ,  Donald Ray Banks ,  Joseph Angelo Benenati ,  Thomas Caulfield ,  Karl Grant Hoebener ,  David P. Watson ,  John Saunders Corbin, Jr.

Inventor： John Acocella ,  Donald Ray Banks ,  Joseph Angelo Benenati ,  Thomas Caulfield ,  Karl Grant Hoebener ,  David P. Watson ,  John Saunders Corbin, Jr.

IPC: H05K103

CPC classification number: B23K1/0008 ,  B23K1/0016 ,  B23K2101/36 ,  B23K2101/40 ,  B23K2101/42 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2924/00013 ,  H01L2924/09701 ,  H05K1/114 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3478 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/0215 ,  H05K2201/10234 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/0195 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0455 ,  H05K2203/082 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49144 ,  H01L2224/29099 ,  H01L2924/014

Abstract: High melting temperature Pb/Sn 95/5 solder balls are connected to copper pads on the bottom of a ceramic chip carrier substrate by low melting temperature eutectic Pb/Sn solder. The connection is made by quick reflow to prevent dissolving Pb into the eutectic solder and raising its melting temperature. Then the module is placed on a fiberglass-epoxy circuit board with the solder balls on eutectic Pb/Sn solder bumps on copper pads of the board. The structure is reflowed to simultaneously melt the solder on both sides of the balls to allow each ball to center between the carrier pad and circuit board pad to form a more symmetric joint. This process results in structure that are more reliable under high temperature cycling. Also, to further improve reliability, the balls are made as large as the I/O spacing allows without bridging beam on balls; the two pads are about the same size with more solder on the smaller pad; the pads are at least 75% of the ball diameter; and the eutectic joints are made as large as possible without bridging between pads. For reliability at even higher temperature cycles or larger substrate sizes columns are used instead of balls.

Abstract translation: 高熔点温度Pb / Sn 95/5焊球通过低熔点共晶Pb / Sn焊料连接到陶瓷芯片载体衬底底部的铜焊盘上。 通过快速回流进行连接，以防止将Pb溶解到共晶焊料中并提高其熔融温度。 然后将模块放置在玻璃纤维 - 环氧树脂电路板上，焊锡球焊接在电路板铜焊盘上的共晶Pb / Sn焊料凸块上。 该结构被回流以同时熔化球的两侧的焊料，以允许每个球在载体垫和电路板垫之间居中以形成更对称的接头。 该过程导致在高温循环下更可靠的结构。 此外，为了进一步提高可靠性，将球制成为尽可能大的I / O间距，而不会在球上桥接梁; 两个焊盘的尺寸大致相同，较小的焊盘上焊料更多; 垫片至少为球直径的75％; 并且使共晶接头制成尽可能大，而不会在焊盘之间桥接。 为了在更高的温度循环或更大的基板尺寸下的可靠性，使用色谱柱代替球。

公开(公告)号：US06472611B1

公开(公告)日：2002-10-29

申请号：US09229622

申请日：1999-01-13

Applicant: Steven O. Dunford

Inventor： Steven O. Dunford

IPC: H05K116

CPC classification number: H05K3/3442 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10727 ,  H05K2201/10992 ,  H05K2201/2036 ,  H05K2203/041 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49146

Abstract: A device and method for insuring the separation between a leadless chip carrier and printed wiring board, comprising aligning and attaching conductive pedestals to contact pads of either member and embedding the pedestals into the solder columns which are used to provide electrical connection. The conductive pedestals are comprised of an electrically conducting metal, solder, alloy or composite which will also provide thermal dissipation in selected designs.

Abstract translation: 一种用于确保无引线芯片载体和印刷线路板之间的分离的装置和方法，包括将导电基座对准并附接到任一构件的接触垫并将基座嵌入用于提供电连接的焊料柱中。 导电基座由导电金属，焊料，合金或复合材料构成，这也将在选定的设计中提供散热。

公开(公告)号：US06454159B1

公开(公告)日：2002-09-24

申请号：US09638145

申请日：2000-08-11

Applicant: Masanori Takushima

Inventor： Masanori Takushima

IPC: B23K3100

CPC classification number: H01L24/11 ,  B23K3/0623 ,  B23K2101/40 ,  H01L2224/11003 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K3/3478 ,  H05K3/3484 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/0338 ,  H01L2224/0401

Abstract: Recesses are formed in a solder transfer plate and filled with solder. Core bumps of an electronic component are brought into contact with the solder in the recesses, and thereby the metal contained in the solder in the recesses is melted. The electrical connecting structure, on which the core bump is coated with solder, is formed by separating the electronic component from the transfer plate.

Abstract translation: 凹槽形成在焊料传递板中并填充有焊​​料。 使电子部件的芯凸起与凹部中的焊料接触，从而使容纳在凹部中的焊料中的金属熔融。 通过将电子部件与转印板分离而形成有芯焊料凸起焊接的电连接结构。

公开(公告)号：US20020095784A1

公开(公告)日：2002-07-25

申请号：US09815804

申请日：2001-03-23

Inventor： Jen-Kuang Fang

IPC: H05K003/00 ,  H01R009/00

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01R4/024 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10977 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T29/49149 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099 ,  H01L2924/013

Abstract: A bumping process for chip scale packaging comprises: providing a chip, the chip having an active surface that has a plurality of bonding pads; sequentially forming an under bump metal (UBM) structure and a leaded bump thereon on each of the bonding pads, wherein the material of the leaded bumps is composed of tin and more than 85% of lead; forming a thermosetting plastic on the active surface that covers the leaded bumps; and grinding the surface of the thermosetting plastic to expose the leaded bumps.

Abstract translation: 用于芯片级封装的凸块工艺包括：提供芯片，该芯片具有具有多个焊盘的有源表面; 在每个接合焊盘上依次形成凸块下金属（UBM）结构和引线凸块，其中引线凸块的材料由锡和超过85％的铅组成; 在活性表面上形成热固性塑料，该表面覆盖有铅凸点; 并研磨热固性塑料的表面以暴露带铅的凸块。

公开(公告)号：US20020092895A1

公开(公告)日：2002-07-18

申请号：US09759113

申请日：2001-01-12

Inventor： Edmund Blackshear ,  Pedro Chalco

IPC: B23K031/02 ,  B23K035/24

CPC classification number: B23K35/262 ,  B23K35/001 ,  B23K35/26 ,  B23K35/30 ,  H01L2224/81825 ,  H01L2924/01322 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  Y02P70/613 ,  H01L2924/00

Abstract: Disclosed is a method to provide a transient liquid phase solder joint by annealing and quenching. The invention allows the attainment of a single phase solder joint at room temperature which will not reflow in subsequent thermal processing above the initial reflow temperature and thus obviates the need for a solder material hierarchy.

Abstract translation: 公开了一种通过退火和淬火来提供瞬态液相焊点的方法。 本发明允许在室温下获得单相焊点，其在随后的热处理中将不会在初始回流温度之上回流，因此避免了对焊料材料层次的需要。