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公开(公告)号：US20200210093A1
公开(公告)日：2020-07-02
申请号：US16278172
申请日：2019-02-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Ping-Chuan Lin , Shii-Yeu Chern , Tai-Yuan Huang , Yi-Hsuan Lin , Chi-Shun Kao
IPC: G06F3/06
Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.
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公开(公告)号：US10678698B2
公开(公告)日：2020-06-09
申请号：US15706757
申请日：2017-09-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
IPC: G06F12/02 , G06F12/08 , G06F3/06 , G06F12/0884
Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The data writing method includes transmitting a command to a host system to obtain a plurality of data, wherein the plurality of data are arranged in a sequence order in the host system, obtaining first data among the plurality of data and obtaining second data after obtaining the first data. The method further includes writing the first data to a corresponding physical page on a first word line among a plurality of word lines, and writing the second data to another corresponding physical page on a second word line among the plurality of word lines, wherein the first and second word lines belong to first and second memory sub-modules, and the first data and the second data are discontinuously arranged in the sequence order. The first and second data may each comprise sub-data, and the sub-data may be written into physical pages on the first and second word lines.
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公开(公告)号：US20200073792A1
公开(公告)日：2020-03-05
申请号：US16168841
申请日：2018-10-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
Abstract: Exemplary embodiments of the disclosure provide a memory management method for a rewritable non-volatile memory module including the following steps. A host write operation is performed to receive a write command from a host system and store a first data corresponding to the write command to a first physical unit. A first updating data corresponding to the host write operation is recorded. A data merge operation is performed to read a second data from a second physical unit and store the second data to a third physical unit. A second updating data corresponding to the data merge operation is recorded. A management information is read from the rewritable non-volatile memory module to a buffer memory and updated in the buffer memory according to the first updating data and the second updating data.
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公开(公告)号：US20200065187A1
公开(公告)日：2020-02-27
申请号：US16153828
申请日：2018-10-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.
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公开(公告)号：US10546640B2
公开(公告)日：2020-01-28
申请号：US15591116
申请日：2017-05-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Tsung-Lin Wu , Te-Chang Tsui , Chien-Fu Lee
Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.
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Patent Agency Ranking
公开(公告)号：US10529426B2
公开(公告)日：2020-01-07
申请号：US15910030
申请日：2018-03-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Sung-Yao Lin , Yueh-Pu Kuo , Yu-Min Hsiao
Abstract: A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data; using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size; and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.
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公开(公告)号：US10522234B2
公开(公告)日：2019-12-31
申请号：US15890326
申请日：2018-02-06
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Hsiang Lin , Yu-Cheng Hsu
Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.
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公开(公告)号：US10475927B2
公开(公告)日：2019-11-12
申请号：US15927088
申请日：2018-03-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hiroshi Watanabe
IPC: G11C8/00 , H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/06 , H01L29/786 , H03K3/84
Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
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公开(公告)号：US20190324904A1
公开(公告)日：2019-10-24
申请号：US16004443
申请日：2018-06-11
Applicant: PHISON ELECTRONICS CORP.
Inventor： Kok-Yong Tan
IPC: G06F12/0804 , G06F12/10
Abstract: A trim command recording method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a write command from a host system; writing a data corresponding to the write command to a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units; and when receiving a trim command from the host system, writing a trim command record corresponding to the trim command into a second physical programming unit of the first physical erasing unit.
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公开(公告)号：US20190318791A1
公开(公告)日：2019-10-17
申请号：US16003114
申请日：2018-06-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Szu-Wei Chen , Yu-Siang Yang
Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.
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