公开(公告)号：US06909054B2

公开(公告)日：2005-06-21

申请号：US10181682

申请日：2001-01-12

Applicant: Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

Inventor： Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H05K1/18 ,  H05K1/16

CPC classification number: H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.

Abstract translation: 多层印刷电路板预先包括在芯基板30中的IC芯片20和设置在IC芯片20的焊盘24上的过渡层38。 由此，可以不使用引线部件和密封树脂将IC芯片电连接到多层印刷电路板。 此外，通过在芯片焊盘24上设置由铜制成的过渡层38，可以防止焊盘24上的树脂残留，并且改善焊盘24和通孔60之间的连接特性以及可靠性。

公开(公告)号：US06376052B1

公开(公告)日：2002-04-23

申请号：US09556860

申请日：2000-04-21

Applicant: Motoo Asai ,  Ken-ichi Shimada ,  Kouta Noda ,  Takashi Kariya ,  Hiroshi Segawa

Inventor： Motoo Asai ,  Ken-ichi Shimada ,  Kouta Noda ,  Takashi Kariya ,  Hiroshi Segawa

IPC: B32B300

CPC classification number: B32B3/00 ,  H05K3/0094 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring.

Abstract translation: 多层印刷布线板由设置有通孔的基板和通过插入层间绝缘树脂层而形成在基板上的布线板，所述通孔具有粗糙的内表面并填充有填料， 通孔中的填充物的暴露部分被覆盖有通孔覆盖导体层，并且形成在其上方的通孔连接到通孔覆盖导体层。在通孔和 填充物，该布线板在通孔和内层电路之间具有令人满意的连接可靠性，并且提供高密度布线。

公开(公告)号：US06376049B1

公开(公告)日：2002-04-23

申请号：US09341689

申请日：1999-07-23

Applicant: Motoo Asai ,  Kenichi Shimada ,  Kouta Noda ,  Takashi Kariya ,  Hiroshi Segawa

Inventor： Motoo Asai ,  Kenichi Shimada ,  Kouta Noda ,  Takashi Kariya ,  Hiroshi Segawa

IPC: B32B300

CPC classification number: B32B3/00 ,  H05K3/0094 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring.

Abstract translation: 多层印刷布线板由设置有通孔的基板和通过插入层间绝缘树脂层而形成在基板上的布线板，所述通孔具有粗糙的内表面并填充有填料， 通孔中的填充物的暴露部分被覆盖有通孔覆盖导体层，并且形成在其上方的通孔连接到通孔覆盖导体层。 在通孔和填料之间不剥离，该布线板在通孔和内层电路之间具有令人满意的连接可靠性，并提供高密度布线。

公开(公告)号：US08829355B2

公开(公告)日：2014-09-09

申请号：US12609447

申请日：2009-10-30

Applicant: Takashi Kariya ,  Kazuhiro Yoshikawa ,  Daiki Komatsu ,  Ramesh Bhandari

Inventor： Takashi Kariya ,  Kazuhiro Yoshikawa ,  Daiki Komatsu ,  Ramesh Bhandari

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/18 ,  H01L23/538 ,  H01L23/13 ,  H01L21/48 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/429 ,  H01L21/486 ,  H01L23/13 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/068 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer printed wiring board includes a core base material having a penetrating portion, a low-thermal-expansion substrate accommodated inside the penetrating portion of the core base material and having a first surface for mounting a semiconductor element and a second surface on the opposite side of the first surface, a first through-hole conductor provided inside the low-thermal-expansion substrate and provided for electrical connection between the first surface and the second surface of the low-thermal-expansion substrate, a filler filled in a gap between the low-thermal-expansion substrate and an inner wall of the core base material, and a wiring layer formed on at least one of the first surface and the second surface of the low-thermal-expansion substrate and having a resin insulation layer and a conductive layer. The wiring layer has a via conductor connecting the first through-hole conductor and the conductive layer.

Abstract translation: 多层印刷布线板包括具有穿透部分的芯基材，容纳在芯基材的穿透部分内的低热膨胀基板，并且具有用于安装半导体元件的第一表面和在相对侧上的第二表面 所述第一通孔导体设置在所述低热膨胀基板内部并且设置用于在所述低热膨胀基板的第一表面和所述第二表面之间的电连接，填充在所述低热膨胀基板之间的间隙中的填料 低热膨胀基板和芯基材的内壁，以及形成在低热膨胀基板的第一表面和第二表面中的至少一个上的布线层，并且具有树脂绝缘层和导电 层。 布线层具有连接第一通孔导体和导电层的通孔导体。

公开(公告)号：US08730647B2

公开(公告)日：2014-05-20

申请号：US12203340

申请日：2008-09-03

Applicant: Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

Inventor： Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

IPC: H05K1/16 ,  H01G4/228 ,  H01L23/522

CPC classification number: H05K1/162 ,  H05K3/0044 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09845 ,  H05K2203/025 ,  H05K2203/1476

Abstract: A printed wiring board includes a capacitor including a dielectric body having a first surface and a second surface, a first electrode provided on the first surface of the dielectric body, and a second electrode provided on the second surface of the dielectric body. The first electrode has an area facing and being smaller than the first surface of the dielectric body, and the second electrode has an area facing and being larger than the second surface of the dielectric body.

Abstract translation: 印刷布线板包括电容器，其包括具有第一表面和第二表面的电介质体，设置在电介质体的第一表面上的第一电极和设置在电介质体的第二表面上的第二电极。 第一电极具有面向并小于电介质体的第一表面的面积，并且第二电极具有面向并大于电介质体的第二表面的面积。

公开(公告)号：US08629550B2

公开(公告)日：2014-01-14

申请号：US13206084

申请日：2011-08-09

Applicant: Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H01L23/48 ,  H05K1/11 ,  H05K7/00

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract translation: 一种印刷电路板，包括芯基板，形成在所述芯基板上并包括第一绝缘层的堆积层，形成在所述第一绝缘层上的导体层和形成在所述导体层上的第二绝缘层，以及一个或 在第一绝缘层上形成更多的布线图案。 导体层包括导体部分，并且导体部分分别具有跨越布线图案彼此面对的切口部分。

公开(公告)号：US08453323B2

公开(公告)日：2013-06-04

申请号：US13234721

申请日：2011-09-16

Applicant: Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

Inventor： Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

IPC: H01K3/10 ,  H05K1/16 ,  H05K7/10 ,  H01L21/00

CPC classification number: H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method for manufacturing a printed circuit board, including providing a core substrate having an electronic component accommodated in the core substrate; forming a positioning mark on the core substrate; forming an interlayer insulating layer over the core substrate, the positioning mark and the electronic component; forming a via hole opening connecting to the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate; and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the electronic component.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，提供具有容纳在所述芯基板中的电子部件的芯基板， 在芯基板上形成定位标记; 在芯基板，定位标记和电子部件之上形成层间绝缘层; 根据芯基板上的定位标记，通过层间绝缘层形成连接到电子部件的通孔开口; 以及在所述层间绝缘层的通孔开口中形成通孔结构，使得所述通孔结构电连接到所述电子部件。

公开(公告)号：US08438727B2

公开(公告)日：2013-05-14

申请号：US12571973

申请日：2009-10-01

Applicant: Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

Inventor： Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

IPC: H01K3/10 ,  H05K3/30

CPC classification number: H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method of manufacturing a multilayer printed circuit board having interlayer insulating layers and conductor layers repeatedly formed on a substrate, via holes formed in the interlayer insulating layers, and establishing electrical connection through the via holes, including containing an electronic component in said substrate, forming a positioning mark on said substrate based on a positioning mark of said electronic component, and conducting working or formation based on the positioning mark of said substrate.

Abstract translation: 一种制造多层印刷电路板的方法，所述多层印刷电路板具有层间绝缘层和导体层，所述多层印刷电路板重复地形成在基板上，通过形成在所述层间绝缘层中的孔，并且通过所述通孔建立与所述基板中包含电子部件的电连接， 基于所述电子部件的定位标记在所述基板上的定位标记，并且基于所述基板的定位标记进行加工或形成。

公开(公告)号：US08373069B2

公开(公告)日：2013-02-12

申请号：US12647015

申请日：2009-12-24

Applicant: Takashi Kariya ,  Daiki Komatsu

Inventor： Takashi Kariya ,  Daiki Komatsu

IPC: H05K1/03

CPC classification number: H05K1/162 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/108 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  Y10T29/4916 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.

Abstract translation: 一种电子部件安装基板，包括由具有第一表面和第二表面的树脂制成的支撑层，在所述支撑层的第一表面上的有机绝缘层，在所述支撑层的第一表面的相对侧上具有第一表面， 与支撑层的第一表面接触，有机层的第一表面上的无机绝缘层，支撑层的第二表面上的导体和在有机层的第二表面上的第一导电电路。 无机层具有第二导电电路和用于将电子部件安装在无机层内部的焊盘。 有机层在有机层内部具有通孔导体并连接第一和第二电路。 支撑层在支撑层内部具有导电柱并连接第一电路和导体。

公开(公告)号：US08334466B2

公开(公告)日：2012-12-18

申请号：US12842431

申请日：2010-07-23

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H05K1/16

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/113 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/49139

Abstract: A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.

Abstract translation: 一种多层印刷电路板，包括芯基板，具有与基板接触的第一表面的积层布线层和第二表面，所述第二表面包括用于安装半导体器件的安装区域，所述堆叠层包括电路 和绝缘层，形成在所述基板的与所述安装区域对应的第一部分中的第一通孔导体，形成在所述基板的第二部分中的第二通孔导体，所述第二通孔导体对应于所述第二表面的除了所述安装 形成在基板的第一部分的处理器核心区域中的区域，第三通孔导体，其对应于设备的处理器核心部分，以及焊盘，设置在第二表面上。 第一导体的间距小于第二导体的间距，第三导体的间距小于第一导体的间距。