公开(公告)号：US11935862B2

公开(公告)日：2024-03-19

申请号：US17354969

申请日：2021-06-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H10B80/00

CPC classification number: H01L24/32 ,  H01L23/481 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H10B80/00 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor structure, a second semiconductor structure opposite to the first semiconductor structure, and an interface layer between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second semiconductor structure includes a plurality of peripheral circuits electrically connected to the memory stack. The interface layer includes single crystalline silicon and a plurality of interconnects between the memory stack and the peripheral circuits.

公开(公告)号：US20230361031A1

公开(公告)日：2023-11-09

申请号：US17738786

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei LIU ,  Yuancheng Yang ,  Wenxi Zhou ,  Kun Zhang ,  Di Wang ,  Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/528 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L23/5283 ,  H01L27/11551 ,  H01L27/11578

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

公开(公告)号：US20230354579A1

公开(公告)日：2023-11-02

申请号：US17731530

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuancheng YANG ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

公开(公告)号：US11647632B2

公开(公告)日：2023-05-09

申请号：US17085305

申请日：2020-10-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Linchun Wu ,  Zhong Zhang ,  Wenxi Zhou ,  Zongliang Huo

IPC: H01L27/1158 ,  H01L25/18 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11582

CPC classification number: H01L27/11582 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/32145

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.

公开(公告)号：US20230131174A1

公开(公告)日：2023-04-27

申请号：US18088419

申请日：2022-12-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H10B43/35 ,  H10B43/40 ,  H10B43/27

Abstract: In an example, a method for forming a three-dimensional (3D) memory device is disclosed. A semiconductor layer is formed. A memory stack on the semiconductor is formed. A channel structure extending through the memory stack and the semiconductor layer is formed. An end of the channel structure abutting the semiconductor layer is exposed. A portion of the channel structure abutting the semiconductor layer is replaced with a semiconductor plug.

公开(公告)号：US11626416B2

公开(公告)日：2023-04-11

申请号：US16881324

申请日：2020-05-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L25/00 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer above a second semiconductor layer at a first side of a substrate and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed. The sacrificial layer is replaced with a first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. A source contact is formed at a second side opposite to the first side of the substrate to be in contact with the second semiconductor layer.

公开(公告)号：US20230059524A1

公开(公告)日：2023-02-23

申请号：US17570123

申请日：2022-01-06

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Xie ,  Di Wang ,  Bingguo Wang ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

公开(公告)号：US11574925B2

公开(公告)日：2023-02-07

申请号：US17228526

申请日：2021-04-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Haojie Song ,  Kun Bao ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A memory stack including interleaved conductive layers and dielectric layers is formed by replacing, through a slit opening, sacrificial layers with conductive layers. A first source contact portion is formed in the slit opening. Simultaneously, a channel local contact opening is formed through a local dielectric layer to expose a channel structure, and a staircase local contact opening is formed through the local dielectric layer to expose one of the conductive layers at a staircase structure on an edge of the memory stack. Also, simultaneously, a channel local contact, a second source contact portion above a first source contact portion in the slit opening, and a staircase local contact are formed, respectively, in the channel local contact opening, the slit opening, and the staircase local contact opening.

公开(公告)号：US11557601B2

公开(公告)日：2023-01-17

申请号：US16913634

申请日：2020-06-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, and a source contact above the memory stack and in contact with the P-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the P-type doped semiconductor layer.

公开(公告)号：US20230005861A1

公开(公告)日：2023-01-05

申请号：US17481838

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanhong Wang ,  Wei Liu ,  Liang Chen ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.