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    CMP process flow for MEMS
    41.
    发明授权
    CMP process flow for MEMS 有权
    MEMS工艺流程

    公开(公告)号：US08124527B2

    公开(公告)日：2012-02-28

    申请号：US13036201

    申请日：2011-02-28

    Applicant: Joseph Damian Gordon Lacey ,  Thomas L. Maguire ,  Vikram Joshi ,  Dennis J. Yost

    Inventor： Joseph Damian Gordon Lacey ,  Thomas L. Maguire ,  Vikram Joshi ,  Dennis J. Yost

    IPC: H01L21/4763

    CPC classification number: B81C1/00095 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0104

    Abstract: The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

    Abstract translation: 本发明一般涉及在线路（BEOL）工艺的互补金属氧化物半导体（CMOS）后端中形成微机电系统（MEMS）悬臂开关。 悬臂开关形成为与结构中的下电极电连通。 下电极可以是毯式沉积和图案化或简单地沉积在底层结构的通孔或沟槽中。 然后通过化学机械抛光或平面化（CMP）将用于下电极的多余材料平坦化。 然后在平坦化的下电极上形成悬臂开关。

    THINNING METHOD AND SILICON WAFER BASED STRUCTURE
    42.
    发明申请
    THINNING METHOD AND SILICON WAFER BASED STRUCTURE 审中-公开
    基于方法和基于硅波的结构

    公开(公告)号：US20110250733A1

    公开(公告)日：2011-10-13

    申请号：US13168375

    申请日：2011-06-24

    Applicant: Vesa-Pekka Lempinen ,  Jari Mäkinen ,  Markku Tilli

    Inventor： Vesa-Pekka Lempinen ,  Jari Mäkinen ,  Markku Tilli

    IPC: H01L21/304 ,  B32B3/00 ,  H01L21/306

    CPC classification number: B81C1/00626 ,  B81B2203/0127 ,  B81C2201/0104 ,  Y10T428/24479

    Abstract: A method for thinning a wafer layer to a predetermined thickness comprises two phases of thinning. A first thinning phase and a second thinning phase, wherein the first thinning phase is a preparatory thinning phase and the second thinning phase is a final thinning phase, so performed that the structure comprising silicon meets as thinned the final thickness as predetermined. Such thinned layer in a wafer for instance, can be used in a sensor to be used in normal sized, micromechanical or even nano-sized devices for the device specific sensing applications in electromechanical devices.

    Abstract translation: 将晶片薄层化为预定厚度的方法包括两个稀化阶段。 第一稀化相和第二稀化相，其中所述第一稀化相是预备性稀化相，并且所述第二稀化相是最终稀化相，因此执行包括硅的结构使预定的最终厚度变薄。 例如，晶片中的这种薄化层可以用于传感器中，以用于在机电装置中用于器件特定感测应用的正常尺寸，微机械或甚至纳米尺寸的装置中。

    Method and apparatus for fabricating structures using chemically selective endpoint detection
    44.
    发明申请
    Method and apparatus for fabricating structures using chemically selective endpoint detection 失效

    公开(公告)号：US20030008519A1

    公开(公告)日：2003-01-09

    申请号：US09900300

    申请日：2001-07-05

    Inventor： Jeffrey J. Peterson ,  Charles E. Hunt

    IPC: H01L021/461

    CPC classification number: H01L21/30604 ,  B81C1/00626 ,  B81C2201/0104 ,  B81C2201/0133 ,  H01L21/30608

    Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.

    Method of manufacturing a semiconductor accelerometer
    45.
    发明授权
    Method of manufacturing a semiconductor accelerometer 失效
    制造半导体加速度计的方法

    公开(公告)号：US5656512A

    公开(公告)日：1997-08-12

    申请号：US457643

    申请日：1995-05-31

    Applicant: Bruce Allan Beitman

    Inventor： Bruce Allan Beitman

    IPC: G01P15/12 ,  B81B3/00 ,  G01P15/08 ,  H01L21/306 ,  H01L29/84 ,  H01L21/3213

    CPC classification number: B81C1/0015 ,  G01P15/0802 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C2201/0104 ,  B81C2201/0136 ,  B81C2201/019 ,  B81C2201/0191 ,  G01P2015/0828

    Abstract: A semiconductor accelerometer is formed by attaching a semiconductor layer to a handle wafer by a thick oxide layer. Accelerometer geometry is patterned in the semiconductor layer, which is then used as a mask to etch out a cavity in the underlying thick oxide. The mask may include one or more apertures, so that a mass region will have corresponding apertures to the underlying oxide layer. The structure resulting from an oxide etch has the intended accelerometer geometry of a large volume mass region supported in cantilever fashion by a plurality of piezo-resistive arm regions to a surrounding, supporting portion of the semiconductor layer. Directly beneath this accelerometer geometry is a flex-accommodating cavity realized by the removal of the underlying oxide layer. The semiconductor layer remains attached to the handle wafer by means of the thick oxide layer that surrounds the accelerometer geometry, and which was adequately masked by the surrounding portion of the top semiconductor layer during the oxide etch step. In a second embodiment support arm regions are dimensioned separately from the mass region, using a plurality of buried oxide regions as semiconductor etch stops.

    Abstract translation: 半导体加速度计是通过用厚的氧化物层将半导体层附着在手柄晶片上形成的。 加速度传感器几何形状在半导体层中图案化，然后将其用作掩模以蚀刻下面的厚氧化物中的空腔。 掩模可以包括一个或多个孔，使得质量区域将具有到下面的氧化物层的对应的孔。 由氧化物蚀刻产生的结构具有通过多个压阻臂区域以半悬臂方式支撑到半导体层的周围的支撑部分的大体积质量区域的预期加速度计几何形状。 直接在该加速度计几何形状之下的是通过去除下面的氧化物层而实现的柔性容纳腔。 半导体层通过围绕加速度计几何形状的厚氧化物层保持附着到处理晶片，并且在氧化物蚀刻步骤期间，半导体层被顶部半导体层的周围部分充分掩蔽。 在第二实施例中，使用多个掩埋氧化物区域作为半导体蚀刻停止件，将支撑臂区域与质量区域分开设计。

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