公开(公告)号：US09390013B2

公开(公告)日：2016-07-12

申请号：US14037512

申请日：2013-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  David W. Cummings ,  Michael S. Siegel ,  Jeffrey A. Stuecheli

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0817 ,  G06F12/0828

Abstract: A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (AP) external to the primary coherent system. The CAPP includes a CAPP directory of contents of a cache memory in the AP that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. In response to the memory access request, the CAPP performs a first determination of a coherence state for the target address and allocates a master machine to service the memory access request in accordance with the first determination. Thereafter, during allocation of the master machine, the CAPP updates the coherence state and performs a second determination of the coherence state. The master machine services the memory access request in accordance with the second determination.

公开(公告)号：US09355035B2

公开(公告)日：2016-05-31

申请号：US14082199

申请日：2013-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Benjiman L. Goodman ,  Jody B. Joyner ,  Stephen J. Powell ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0864 ,  G06F2212/621 ,  Y02D10/13

Abstract: A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

Abstract translation: 集合关联缓存由存储器控制器管理，存储器控制器将修改（脏）高速缓存行的回写指令放入虚拟写入队列中，确定包含修改的高速缓存行的集合的数量何时大于高水位标记，并且升高一个 回读指令优先于读取操作。 当修改集合的数量小于低水位时，控制器可以将优先级恢复为正常。 在其中系统存储器件包括等级组的实施例中，可以基于等级组映射一致等级。 超过不同阈值的等级组中挂起的写入次数还可以是触发提高回写优先级的要求。 可以使用脏向量来提供对应集合包含修改的高速缓存行的指示，特别是相应集合的最近最少使用的段。

公开(公告)号：US09298626B2

公开(公告)日：2016-03-29

申请号：US14037879

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

IPC: G06F13/12 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0828 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

Abstract: Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

Abstract translation: 具有事务性存储器的计算环境中的高速缓存行可使用一致性模式进行配置。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 当以全线一致性模式访问高速缓存行的事务导致事务中止时，如果高速缓存行是高冲突高速缓存行，则高速缓存行可以被置于子行一致性模式。 高速缓存行可以与冲突地址检测表中的计数器相关联，每当检测到高速缓存行的事务冲突时，它将递增。 当计数器满足诸如达到阈值的高冲突标准时，高速缓存行可以是高冲突高速缓存行。 当满足复位标准时，高速缓存行可以返回到全线一致性模式。

公开(公告)号：US09244724B2

公开(公告)日：2016-01-26

申请号：US13967795

申请日：2013-08-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0828

Abstract: In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

公开(公告)号：US20150331796A1

公开(公告)日：2015-11-19

申请号：US14312157

申请日：2014-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  HUGH SHEN ,  DEREK E. WILLIAMS

IPC: G06F12/08

CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/283 ,  G06F2212/62

Abstract: In response to execution in a memory transaction of a transactional load instruction that speculatively binds to a value held in a store-through upper level cache, a processor core sets a flag, transmits a transactional load operation to a store-in lower level cache that tracks a target cache line address of a target cache line containing the value, monitors, during a core TM tracking interval, the target cache line address for invalidation messages from the store-in lower level cache until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the target cache line address, and responsive to receipt during the core TM tracking interval of an invalidation message indicating presence of a conflicting snooped operation, resets the flag. At termination of the memory transaction, the processor core fails the memory transaction responsive to the flag being reset.

Abstract translation: 响应于在事务加载指令的存储器事务中执行，该事务性加载指令推测性地绑定到存储在上级高速缓存中的值，处理器核心设置标志，将事务加载操作发送到存储在下级缓存中， 跟踪包含该值的目标高速缓存行的目标高速缓存线地址，在核心TM跟踪间隔期间监视来自存储在较低级别高速缓存中的无效消息的目标高速缓存行地址，直到存储的较低级高速缓存信号 存储的低级缓存器承担了跟踪目标高速缓存线地址的责任，并且响应于在核心TM跟踪间隔期间的接收指示存在冲突的窥探操作的无效消息，复位该标志。 在存储器事务终止时，处理器核心响应于标志被复位而失败存储器事务。

公开(公告)号：US09146872B2

公开(公告)日：2015-09-29

申请号：US13776968

申请日：2013-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  David W. Cummings ,  Michael S. Siegel ,  Jeff A. Stuecheli

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0831

Abstract: In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from AP.

Abstract translation: 响应于在连接的附属处理器代理（CAPP）处的附接处理器处接收到存储器访问请求和期望的一致性状态，CAPP确定正在处理冲突的请求。 响应于确定CAPP正在服务于冲突请求并且预期状态匹配，CAPP的主机被分配为驻留状态以在完成冲突请求的服务之后对存储器访问请求进行服务。 驻留状态可防止CAPP对系统结构上窥探的进一步冲突的请求进行维护。 响应于冲突请求的服务完成，主机转移到驻留状态，并在系统结构上发出与从AP接收到的存储器访问请求相对应的存储器访问请求。

公开(公告)号：US09141545B2

公开(公告)日：2015-09-22

申请号：US14557715

申请日：2014-12-02

Applicant: ARM Finance Overseas Limited

Inventor： William Lee ,  Thomas Benjamin Berg

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0871 ,  G06F2212/507 ,  G06F2212/621 ,  Y02D10/13

Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.

Abstract translation: 设置在多核微处理器中的高速缓存一致性管理器包括请求单元，干预单元，响应单元和接口单元。 请求单元接收相干请求并有选择地发出响应的推测请求。 接口单元选择性地将推测请求转发到存储器。 接口单元至少包括三个表。 第一个表中的每个条目表示第二个表的索引。 第二个表中的每个条目表示第三个表的索引。 当对相关干预消息的响应存储在第一表中但在接口单元接收到推测请求之前，分配第一表中的条目。 当推测请求存储在接口单元中时，分配第二个表中的条目。 当向内存发出推测请求时，会分配第三个表中的条目。

公开(公告)号：US09135174B2

公开(公告)日：2015-09-15

申请号：US13686454

申请日：2012-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  David W. Cummings ,  Michael S. Siegel ,  Jeff A. Stuecheli

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0831

Abstract: In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from the AP.

Abstract translation: 响应于在连接的附属处理器代理（CAPP）处的附接处理器处接收到存储器访问请求和期望的一致性状态，CAPP确定正在处理冲突的请求。 响应于确定CAPP正在服务于冲突请求并且预期状态匹配，CAPP的主机被分配为驻留状态以在完成冲突请求的服务之后对存储器访问请求进行服务。 驻留状态可防止CAPP对系统结构上窥探的进一步冲突的请求进行维护。 响应于冲突请求的服务完成，主机转移到驻留状态，并在系统结构上发出与从AP接收到的存储器访问请求相对应的存储器访问请求。

公开(公告)号：US09122617B2

公开(公告)日：2015-09-01

申请号：US12276069

申请日：2008-11-21

Applicant: Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

Inventor： Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/621

Abstract: Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss. As such, the other L2 level cache memory units serve the original L2 cache memory unit as pseudo caches.

Abstract translation: 具体地说，在本发明中，高速缓冲存储器单元可以被指定为公共层级内的另一高速缓冲存储器单元的伪高速缓冲存储器单元。 例如，在层次结构的高速缓存级L2上的高速缓存存储器单元“X”处的高速缓存未命中的情况下，将请求发送到高速缓存级L3（外部）上的高速缓冲存储器单元以及一个或多个其他高速缓冲存储器单元 在缓存级L2上。 L2级缓存单元返回搜索结果作为命中或未命中。 它们通常不会搜索L3，也不会用L3结果写回（即使结果是错过）。 在这个程度上，如果所有的L2都错过，只有请求的直接起始点才会用L3结果写回来。 这样，其他L2级高速缓冲存储器单元用作原始高速缓存存储器单元作为伪高速缓存。

公开(公告)号：US20150205722A1

公开(公告)日：2015-07-23

申请号：US14159151

申请日：2014-01-20

Applicant: International Business Machines Corporation

Inventor： Lawrence Y. Chiu ,  Yang Liu ,  Paul H. Muench ,  Timothy L. Toohey

IPC: G06F12/08 ,  G06F11/20 ,  G06F12/12

CPC classification number: G06F11/2043 ,  G06F11/1658 ,  G06F11/2033 ,  G06F11/2038 ,  G06F11/2046 ,  G06F11/2094 ,  G06F12/0817 ,  G06F12/0828 ,  G06F12/121 ,  G06F2201/885 ,  G06F2211/1009 ,  G06F2212/621 ,  H04L67/2842

Abstract: For a high availability cache, a cache module obtains permission to manage the cache in response to a failover event in a server cluster by communicating a cache coherency token. An update module rebuilds a cache directory from data stored in the cache and accesses the cache without reloading the data stored in the cache.

Abstract translation: 对于高可用性缓存，高速缓存模块通过传送高速缓存一致性令牌来获得管理缓存的权限，以响应服务器群集中的故障切换事件。 更新模块从存储在缓存中的数据重建缓存目录，并访问高速缓存，而不重新加载存储在缓存中的数据。