公开(公告)号：US20110155441A1

公开(公告)日：2011-06-30

申请号：US12783851

申请日：2010-05-20

Applicant: Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC: H05K1/11 ,  H05K3/12

CPC classification number: H05K3/06 ,  H05K1/0298 ,  H05K3/465 ,  H05K2201/0347 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A process for fabricating a circuit board is provided. A circuit substrate having a first surface and a first circuit layer is provided. A first dielectric layer having a second surface is formed on the circuit substrate and covers the first surface and the first circuit layer. An antagonistic activation layer is formed on the second surface. The antagonistic activation layer is irradiated by a laser beam to form at least a blind via extended from the antagonistic activation layer to the first circuit layer and an intaglio pattern. A first conductive layer is formed inside the blind via. A second conductive layer is formed in the intaglio pattern and the blind via. The second conductive layer covers the first conductive layer and is electrically connected with the first circuit layer through the first conductive layer. The antagonistic activation layer is removed to expose the second surface.

Abstract translation: 提供一种制造电路板的工艺。 提供具有第一表面和第一电路层的电路基板。 具有第二表面的第一电介质层形成在电路基板上并覆盖第一表面和第一电路层。 在第二表面上形成拮抗活化层。 通过激光束照射拮抗激活层，以形成从拮抗活化层延伸到第一电路层和凹版图案的至少盲目通孔。 在盲通孔内形成第一导电层。 在凹版图案和盲孔中形成第二导电层。 第二导电层覆盖第一导电层，并通过第一导电层与第一电路层电连接。 去除拮抗活化层以暴露第二表面。

公开(公告)号：US07877871B2

公开(公告)日：2011-02-01

申请号：US12230280

申请日：2008-08-27

Applicant: Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo ,  Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume

Inventor： Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo ,  Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume

IPC: H05K3/02 ,  G03G15/16

CPC classification number: H05K3/207 ,  G03G15/6591 ,  G03G2215/00523 ,  H05K1/095 ,  H05K3/1266 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2201/09781 ,  H05K2203/0517 ,  H05K2203/105 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An image forming apparatus comprises an exposure unit forming an electrostatic latent image on a photo conductor based on image information, a developing unit developing the electrostatic latent image by toner made of formation material of a circuitry layer, and an electrostatic transferring unit transferring a toner image on the photo conductor onto a substrate. The toner image is transferred so as to cover at least a part of a conductor layer formed on the substrate. At this time, excessive charges caused in the conductor layer accompanying the start of the transfer of the toner image are removed. Alternatively, charges of which polarity is reverse to that of the toner are added to the conductor layer. These allow the circuitry layer to be formed to have a desired pattern favorably and securely on the conductor layer.

Abstract translation: 图像形成装置包括基于图像信息在光导体上形成静电潜像的曝光单元，通过电路层的形成材料制成的调色剂来显影静电潜像的显影单元和传送调色剂图像的静电转印单元 在光导体上的基片上。 转印调色剂图像以覆盖形成在基板上的导体层的至少一部分。 此时，伴随着调色剂图像的转印开始导致的导体层中引起的过多的电荷被去除。 或者，将与该调色剂相反极性的电荷加到导体层中。 这些允许电路层形成为在导体层上有利地并且牢固地具有期望的图案。

公开(公告)号：US07875804B1

公开(公告)日：2011-01-25

申请号：US11535712

申请日：2006-09-27

Applicant: Jeffrey M. Tronnes ,  Cedar Decker ,  Brett L. Haugen

Inventor： Jeffrey M. Tronnes ,  Cedar Decker ,  Brett L. Haugen

IPC: H05K1/00

CPC classification number: G11B5/484 ,  G11B5/4853 ,  H05K1/056 ,  H05K3/244 ,  H05K3/421 ,  H05K3/44 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09554 ,  H05K2201/0969 ,  H05K2203/1184

Abstract: A method for forming an electrical interconnect on an integrated lead suspension or suspension component of the type having a stainless steel layer, a conductive lead layer and an insulator layer separating the stainless steel and conductive lead layers. An aperture is formed through only the insulator layer to expose the stainless steel layer at an interconnect site. An interconnect mask is applied around the interconnect site. A first conductive material is electroplated onto the stainless steel layer at the interconnect site to form a plated interconnect between the spring metal layer and the conductive lead layer. The mask is then removed. An electrical interconnect between the stainless steel and conductive lead layers including an aperture only through the insulator layer and an electroplated conductive material interconnect extending between both the spring metal layer and the conductive lead layer.

Abstract translation: 一种用于在具有不锈钢层，导电引线层和分离不锈钢和导电引线层的绝缘体层的类型的集成引线悬置或悬挂部件上形成电互连的方法。 仅通过绝缘体层形成孔，以在互连部位露出不锈钢层。 在互连站点周围应用互连掩模。 将第一导电材料电镀在互连部位的不锈钢层上，以在弹簧金属层和导电引线层之间形成电镀互连。 然后取下面具。 不锈钢和导电引线层之间的电互连包括仅通过绝缘体层的孔和在弹簧金属层和导电引线层之间延伸的电镀导电材料互连。

公开(公告)号：US07847318B2

公开(公告)日：2010-12-07

申请号：US12406009

申请日：2009-03-17

Applicant: Naohiro Hirose ,  Honjin En

Inventor： Naohiro Hirose ,  Honjin En

IPC: H01L29/40 ,  H05K7/20

CPC classification number: H01L29/40 ,  H01L21/4763 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/03 ,  H05K3/064 ,  H05K3/244 ,  H05K3/382 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09681 ,  H05K2203/1178

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 μm. The reason is as follows. If the diameter of the mesh hole is less than 75 μm, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 μm, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 μm. The reason is as follows. If the distance is less than 100 μm, the solid layer cannot function. If the distance exceeds 2000 μm, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Abstract translation: 上固体层35和上固体层59的网孔35a和59a形成为彼此重叠，使得层间树脂绝缘层50的绝缘性能不降低。 这里，每个网孔的直径优选为75〜300μm。 原因如下。 如果网孔的直径小于75μm，则难以将上，下网孔叠置在一起。 如果直径超过300μm，则层间树脂绝缘层的绝缘性变差。 此外，网孔之间的距离优选为100〜2000μm。 原因如下。 如果距离小于100μm，则固体层不能起作用。 如果距离超过2000μm，则发生层间树脂绝缘膜的绝缘性的劣化。

公开(公告)号：US07829793B2

公开(公告)日：2010-11-09

申请号：US11485912

申请日：2006-07-13

Applicant: Christopher Schreiber ,  Christopher Dunn

Inventor： Christopher Schreiber ,  Christopher Dunn

IPC: H05K1/00

CPC classification number: H05K1/00 ,  G11B5/486 ,  H05K1/056 ,  H05K3/388 ,  H05K3/44 ,  H05K2201/0347 ,  H05K2201/09554 ,  H05K2201/09827 ,  Y10T29/49004 ,  Y10T29/49007 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49224 ,  Y10T428/30 ,  Y10T428/31678

Abstract: An additive process disk drive suspension interconnect, and method therefor is provided. The interconnect has a metal grounding layer of typically stainless steel or copper metallized stainless steel, a metal conductive layer and an insulative layer between the metal grounding layer and the conductive metal layer. A circuit component such as a slider is electrically connected to the conductive layer along a grounding path from the circuit component and the conductive layer to the metal grounding layer through an aperture in the insulative layer. For improved electrical connection a tie layer is provided through the insulative layer onto the grounding layer in bonding relation with the ground layer. A conductor is deposited onto both the conductive metal layer and the tie layer in conductive metal layer and tie layer bonding relation, and the circuit component is thus bonded to the grounding layer by the conductor.

Abstract translation: 提供了一种附加处理磁盘驱动器悬挂互连及其方法。 互连具有通常为不锈钢或铜金属化不锈钢的金属接地层，金属导电层和金属接地层与导电金属层之间的绝缘层。 诸如滑块的电路部件沿着从电路部件和导电层到金属接地层的通过绝缘层的孔的接地路径电连接到导电层。 为了改善电连接，通过绝缘层将接合层提供到与接地层结合的接地层上。 导电体以导电金属层和连接层结合关系沉积在导电金属层和连接层两者上，并且电路部件因此被导体结合到接地层。

公开(公告)号：US20100263917A1

公开(公告)日：2010-10-21

申请号：US12630580

申请日：2009-12-03

Applicant: Soon Yeong Heo ,  Seong Sil Park

Inventor： Soon Yeong Heo ,  Seong Sil Park

IPC: H05K1/00 ,  C25D5/02

CPC classification number: H05K1/095 ,  H05K1/0393 ,  H05K3/246 ,  H05K2201/0154 ,  H05K2201/0347

Abstract: A method of preparing printed circuit boards (PCB) or flexible printed circuit boards (FPCB) by direct printing includes: 1) a step of printing a pattern on substrate with a paste composition including conductive particles, polyamic acid as binder and solvent; 2) a step of baking the printed substrate to imidize the polyamic acid; and 3) a step of electro-plating the printed substrate. Printed circuit boards (PCB) or flexible printed circuit boards (FPCB) are produced by applying an addition method of direct printing while to simplify processes, to save time and cost, and to minimize waste.

Abstract translation: 通过直接印刷制备印刷电路板（PCB）或柔性印刷电路板（FPCB）的方法包括：1）使用包含导电颗粒，聚酰胺酸作为粘合剂和溶剂的浆料组合物在基板上印刷图案的步骤; 2）烘烤印刷基板以酰亚胺化聚酰胺酸的步骤; 和3）电镀印刷基板的步骤。 印刷电路板（PCB）或柔性印刷电路板（FPCB）通过应用直接印刷的添加方法来生产，以简化工艺流程，节省时间和成本，并尽量减少浪费。

公开(公告)号：US07761980B2

公开(公告)日：2010-07-27

申请号：US11441140

申请日：2006-05-26

Applicant: Hiroshi Ota

Inventor： Hiroshi Ota

IPC: H01R43/00 ,  B41J2/015 ,  H05K1/00

CPC classification number: B41J2/161 ,  B41J2/14233 ,  B41J2/1623 ,  B41J2/1637 ,  B41J2/1643 ,  B41J2002/14459 ,  B41J2002/14491 ,  B41J2202/18 ,  B41J2202/20 ,  H05K1/095 ,  H05K3/107 ,  H05K3/1241 ,  H05K3/1258 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2201/09036 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49401

Abstract: The method manufactures a wiring substrate. The method comprises: a recess section forming step of forming recess sections corresponding to a prescribed wiring pattern, on a substrate; a filling step of filling a conductive paste containing thinner, into the recess sections; a curing step of causing the conductive paste filled in the recess sections in the filling step to contract, by drying and curing; and a plating step of forming a wiring conductor serving as the wiring pattern, by performing a plating process using the conductive paste in contact with at least a portion of an inner circumferential face of the recess sections, as at least one of a catalyst and a current feed layer.

Abstract translation: 该方法制造布线基板。 该方法包括：在基板上形成对应于规定布线图案的凹部的凹部形成工序; 填充步骤，将含有稀释剂的导电膏填充到所述凹部中; 固化步骤，通过干燥和固化使填充步骤中的凹部中填充的导电膏收缩; 以及电镀步骤，形成用作布线图案的布线导体，通过使用与凹部的内周面的至少一部分接触的导电浆料进行电镀处理，作为催化剂和 当前进料层。

公开(公告)号：US20100101838A1

公开(公告)日：2010-04-29

申请号：US12649038

申请日：2009-12-29

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/02

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为具有15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US20100059785A1

公开(公告)日：2010-03-11

申请号：US12551893

申请日：2009-09-01

Applicant: SHEN BO LIN ,  PIN CHUAN CHEN ,  CHAO HSIUNG CHANG ,  CHIEN MIN CHEN

Inventor： SHEN BO LIN ,  PIN CHUAN CHEN ,  CHAO HSIUNG CHANG ,  CHIEN MIN CHEN

IPC: H01L33/00 ,  H01L21/56

CPC classification number: H01L33/486 ,  H01L23/3121 ,  H01L23/3735 ,  H01L24/48 ,  H01L33/64 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/4061 ,  H05K2201/0347 ,  H05K2201/0355 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of fabricating a light emitting device initially forms a copper clad ceramic board of the light emitting device using hot-pressing technique at high temperature and photolithography process. Next, a circuit of the light emitting device is formed using die bonding and wire bonding/flip-chip processes. Finally, the light emitting device is sealed using transfer molding or injection molding process.

Abstract translation: 一种制造发光器件的方法最初在高温和光刻工艺中使用热压技术形成发光器件的铜包层陶瓷板。 接下来，使用芯片接合和引线键合/倒装芯片工艺形成发光器件的电路。 最后，使用传递模塑或注射成型工艺密封发光器件。

公开(公告)号：US20100025080A1

公开(公告)日：2010-02-04

申请号：US12512588

申请日：2009-07-30

Applicant: Se-Ho PARK ,  Ki-Huyn KIM ,  Seok-Myong KANG ,  Young-Min LEE

Inventor： Se-Ho PARK ,  Ki-Huyn KIM ,  Seok-Myong KANG ,  Young-Min LEE

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K3/246 ,  H05K1/092 ,  H05K1/095 ,  H05K2201/0347 ,  H05K2203/1131 ,  Y10T29/49155

Abstract: A Printed Circuit Board (PCB) and a method for manufacturing the same are provided. A circuit pattern is formed by printing conductive ink/paste on a substrate, and sintering a layer of the conductive ink or curing a layer of the conductive paste by applying heat. A primary plating layer is formed through electroless plating or electrolytic plating of a high-melting point metal on the circuit pattern. A secondary plating layer is formed through electroless plating or electrolytic plating of a precious metal on the primary plating layer to improve wetting with solder.

Abstract translation: 提供印刷电路板（PCB）及其制造方法。 通过在基板上印刷导电油墨/糊料，并且通过加热来烧结导电油墨层或固化导电浆料层而形成电路图案。 通过电路图案上的高熔点金属的化学镀或电解电镀形成初级镀层。 通过在主镀层上的贵金属的化学镀或电解电镀形成二次镀层，以改善用焊料的润湿。