公开(公告)号：US20110220397A1

公开(公告)日：2011-09-15

申请号：US13113229

申请日：2011-05-23

Applicant: Masataka Mizukoshi ,  Yoshikatsu Ishizuki

Inventor： Masataka Mizukoshi ,  Yoshikatsu Ishizuki

IPC: H05K1/02 ,  B32B38/10 ,  B32B37/06 ,  B32B37/10 ,  H05K3/00 ,  B23K31/02

CPC classification number: H05K3/20 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K1/142 ,  H05K3/4658 ,  H05K3/4694 ,  H05K2201/0108 ,  H05K2201/0352 ,  H05K2201/09972 ,  H05K2203/025 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T156/1052 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/16225

Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.

Abstract translation: 电子部件的制造方法包括在下层上形成树脂层，将包含形成在其一个主表面上的图案的导体板压在树脂层上，将图案嵌入树脂层中，进行抛光，化学机械 通过在导体板的另一个主表面上使用金刚石钻头进行抛光或切割，直到出现树脂层，并将图案留在树脂层中作为导体图案。

公开(公告)号：US07986495B2

公开(公告)日：2011-07-26

申请号：US12369029

申请日：2009-02-11

Applicant: Katsutoshi Kamei ,  Voonyee Ho

Inventor： Katsutoshi Kamei ,  Voonyee Ho

IPC: G11B21/16

CPC classification number: H05K1/0248 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0245 ,  H05K1/056 ,  H05K2201/0352 ,  H05K2201/09672 ,  H05K2201/09727

Abstract: A first insulating layer is formed on a suspension body, and a write wiring trace and a read wiring trace are formed on the first insulating layer. A second insulating layer is formed on the first insulating layer so as to cover the wiring traces. A write wiring trace and a read wiring trace are formed on the second insulating layer. A third insulating layer is formed on the second insulating layer so as to cover the wiring traces. The width of the wiring trace is larger than the width of the wiring trace, and the width of the wiring trace is larger than the width of the wiring trace.

Abstract translation: 在悬架体上形成第一绝缘层，在第一绝缘层上形成写入布线迹线和读取布线迹线。 在第一绝缘层上形成第二绝缘层以覆盖布线迹线。 写入布线迹线和读取布线迹线形成在第二绝缘层上。 在第二绝缘层上形成第三绝缘层以覆盖布线迹线。 布线的宽度大于布线的宽度，布线的宽度大于布线的宽度。

公开(公告)号：US20110168435A1

公开(公告)日：2011-07-14

申请号：US12686775

申请日：2010-01-13

Applicant: ALAN L. BARRY ,  ELI B. SMITH ,  BROOKS S. MANN ,  NICHOLAS HAYDEN HERRON ,  MARK D. KORICH ,  DAVID TANG ,  CINDY CHOU

Inventor： ALAN L. BARRY ,  ELI B. SMITH ,  BROOKS S. MANN ,  NICHOLAS HAYDEN HERRON ,  MARK D. KORICH ,  DAVID TANG ,  CINDY CHOU

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K1/117 ,  H05K1/0265 ,  H05K2201/0352 ,  H05K2201/0919

Abstract: A printed circuit board includes, but is not limited to, a plurality of electrically conductive layers and a plurality of dielectric layers. Each dielectric layer is interposed between adjacent conductive layers to form a body of alternate conductive layers and dielectric layers. At least one of the electrically conductive layers protrudes beyond an end of the body.

Abstract translation: 印刷电路板包括但不限于多个导电层和多个电介质层。 每个电介质层插入相邻的导电层之间以形成交替导电层和电介质层的主体。 至少一个导电层突出超过主体的端部。

公开(公告)号：US20110155442A1

公开(公告)日：2011-06-30

申请号：US12975703

申请日：2010-12-22

Applicant: Tomoko YAMADA

Inventor： Tomoko YAMADA

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/4682 ,  H05K2201/0352 ,  H05K2201/094 ,  H05K2201/09827 ,  H01L2224/0401

Abstract: A multilayer wiring board has a structure in which vias are formed on an inner wiring layer in directions toward both surfaces of the inner wiring layer, respectively, and lands are each defined in the inner wiring layer at a position to be connected to one of the vias, each of the lands having a side surface formed in a tapered shape. The lands include first lands and second lands, and the vias include a via connected to a surface on a smaller diameter side of the first land, and a via connected only to a surface on a larger diameter side of the second land. The size of the surface of the larger diameter side of the second land is equal to the size of the surface of the smaller diameter side of the first land.

Abstract translation: 多层布线基板具有分别在内部布线层上沿着内部布线层的两个表面的方向形成通孔的结构，并且在内部布线层中，在与第一布线层 通孔中的每一个具有形成为锥形的侧表面。 焊盘包括第一焊盘和第二焊盘，并且通孔包括连接到第一焊盘的较小直径侧的表面的通孔以及仅连接到第二焊盘的较大直径侧的表面的通孔。 第二焊盘的较大直径侧的表面的尺寸等于第一焊盘的较小直径侧的表面的尺寸。

公开(公告)号：US20110154659A1

公开(公告)日：2011-06-30

申请号：US12984074

申请日：2011-01-04

Applicant: James David Britton ,  Jorge Eduardo Martinez-Vargas, JR.

Inventor： James David Britton ,  Jorge Eduardo Martinez-Vargas, JR.

IPC: H05K3/34

CPC classification number: H05K3/3447 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0352 ,  H05K2201/062 ,  H05K2201/09309 ,  Y10T29/49144

Abstract: Apparatuses and methods that provide for enhanced connections between PTHs of multi-layer PCBs and electronic component leads, pins or the like. The apparatuses and methods improve the likelihood that the PTHs are completely filled with solder thereby advantageously allowing the PCBs to exhibit high mechanical and electrical reliability. Complete filling of PTHs is achieved by configuring the electrically conductive layers within the multi-layer PCB stack in a manner that reduces the heat sinking effects of the layers during the soldering process. In this regard, the PTHs may not directly contact all of the internal ground or power planes, so the heat sinking or heat transfer effects are reduced. This feature enables molten solder to substantially or completely fill an entire PTH before freezing.

Abstract translation: 提供多层PCB的PTH和电子元件引线，引脚等之间的增强连接的装置和方法。 这些装置和方法提高了PTH完全填充焊料的可能性，从而有利地允许PCB显示出高的机械和电气可靠性。 通过在多层PCB堆叠内配置导电层，以减少焊接过程中各层的散热效应的方法来实现PTH的完全填充。 在这方面，PTH可能不直接接触所有内部地面或电力平面，因此减少了散热或传热效应。 该特征使得熔融焊料在冷冻之前基本上或完全填充整个PTH。

公开(公告)号：US20110085306A1

公开(公告)日：2011-04-14

申请号：US12901104

申请日：2010-10-08

Applicant: Ayao NIKI

Inventor： Ayao NIKI

IPC: H05K1/02

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A coreless multilayer printed wiring board including a coreless layer having an opening, a conductive film formed on an upper surface of the coreless layer and closing one end of the opening of the coreless layer, a via-hole formed in the opening of the coreless layer, a first resin layer formed on the coreless layer and the conductive film and having an opening reaching to the conductive film, a via-hole formed in the opening of the first resin layer, a second resin layer formed on the upper surface of the first resin layer and having an opening, a via-hole formed in the opening of the second resin layer. The via-holes formed in the first and second resin layers are open in the direction opposite to the direction in which the via-hole formed in the coreless layer is open.

Abstract translation: 一种无芯多层印刷线路板，包括具有开口的无芯层，形成在无芯层的上表面上并封闭无芯层的开口的一端的导电膜，形成在无芯层的开口中的通孔 形成在无芯层和导电膜上并具有到达导电膜的开口的第一树脂层，形成在第一树脂层的开口中的通孔，形成在第一树脂层的上表面上的第二树脂层 树脂层并具有开口，形成在第二树脂层的开口中的通孔。 形成在第一和第二树脂层中的通孔在与形成在无芯层中的通孔开放的方向相反的方向上是开放的。

公开(公告)号：US20110075392A1

公开(公告)日：2011-03-31

申请号：US12568941

申请日：2009-09-29

Applicant: Daryl Weispfennig ,  Bradley Schumacher ,  Kwong Kei Chin

Inventor： Daryl Weispfennig ,  Bradley Schumacher ,  Kwong Kei Chin

IPC: H05K1/14 ,  H05K3/34 ,  H05K1/00

CPC classification number: H05K1/0203 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K3/202 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09881 ,  H05K2201/09972 ,  H05K2201/10166 ,  H05K2201/10689 ,  H05K2203/175 ,  Y02P70/611 ,  Y10T29/49126 ,  H01L2924/00

Abstract: An integrated circuit assembly includes a first electrically conductive sheet, a second electrically conductive sheet electrically isolated from the first electrically conductive sheet, a non-conductive material disposed between the first and second electrically conductive sheets, an electrical trace disposed on the non-conductive material and electrically isolated from the first and second electrically conductive sheets, and an integrated circuit having at least one lead directly connected to the first electrically conductive sheet, at least one lead directly connected to the second electrically conductive sheet, and at least one lead electrically connected to the electrical trace. Other integrated circuit assemblies and method for making integrated circuit assemblies are also disclosed.

Abstract translation: 集成电路组件包括第一导电片，与第一导电片电隔离的第二导电片，设置在第一和第二导电片之间的非导电材料，设置在非导电材料上的电迹线 并且与第一和第二导电片电隔离，以及集成电路，其具有直接连接到第一导电片的至少一个引线，直接连接到第二导电片的至少一个引线，以及至少一个引线电连接 到电痕迹。 还公开了用于制造集成电路组件的其它集成电路组件和方法。

公开(公告)号：US20110061905A1

公开(公告)日：2011-03-17

申请号：US12654446

申请日：2009-12-18

Applicant: Mi Sun Hwang ,  Jae Joon Lee ,  Myung Sam Kang

Inventor： Mi Sun Hwang ,  Jae Joon Lee ,  Myung Sam Kang

IPC: H05K1/03 ,  H05K3/36

CPC classification number: H05K3/10 ,  H05K1/0271 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/09136

Abstract: There is provided a printed circuit board. The printed circuit board may be configured to include: a core layer in which a bending prevention portion of at least two layers is interposed between a plurality of insulating members and includes metal layers having different thermal expansion coefficients is disposed; a circuit pattern that is formed so as to have a desired pattern on at least one of the inside of the core layer and an outer face of the core layer; and an insulating layer that is formed on the core layer and includes an opening portion that exposes the circuit pattern, and a method of manufacturing the printed circuit board. According to the above-described printed circuit board and the method of manufacturing the printed circuit board, by disposing a bending prevention portion inside the printed circuit board, a printed circuit board capable of improving the progress rate and the productivity and a method of manufacturing the printed circuit board can be provided.

Abstract translation: 提供了印刷电路板。 印刷电路板可以被构造为包括：芯层，其中至少两层的弯曲防止部分插入在多个绝缘构件之间并且包括具有不同热膨胀系数的金属层; 形成为在芯层的内部和芯层的外表面中的至少一个上具有期望图案的电路图案; 以及形成在芯层上并包括露出电路图案的开口部分的绝缘层，以及制造印刷电路板的方法。 根据上述印刷电路板和印刷电路板的制造方法，通过在印刷电路板内设置弯曲防止部，能够提高进度和生产率的印刷电路板，以及制造印刷电路板的方法 可以提供印刷电路板。

公开(公告)号：US07907390B2

公开(公告)日：2011-03-15

申请号：US11693316

申请日：2007-03-29

Applicant: Shin-ya Nakano ,  Yoh Takano ,  Tetsuro Sawai ,  Ryosuke Usui

Inventor： Shin-ya Nakano ,  Yoh Takano ,  Tetsuro Sawai ,  Ryosuke Usui

IPC: H01L23/34 ,  H05K5/00 ,  H05K7/00

CPC classification number: H01L23/142 ,  H01L23/3737 ,  H01L23/467 ,  H01L23/498 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0203 ,  H05K1/0265 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/10969 ,  H05K2203/0369 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A circuit device includes a metal substrate; and a plurality of circuit elements, mounted on the metal substrate, which electrically connects to the metal substrate. The metal substrate is made of a copper plate of high thermal conductivity. The metal substrate is demarcated into a plurality of sections by insulating films added with a filler for enhancing the thermal conductivity in resin. The circuit elements, which have respective independent operating potentials on a side of the metal substrate of the circuit elements, are respectively provided on separated copper plates.

Abstract translation: 电路装置包括金属基板; 以及多个电路元件，安装在与金属基板电连接的金属基板上。 金属基板由具有高导热性的铜板制成。 通过添加有填充剂的绝缘膜将金属基板划分为多个部分，以提高树脂中的导热性。 在电路元件的金属基板的一侧具有各自的独立工作电位的电路元件分别设置在分离的铜板上。

公开(公告)号：US07902465B1

公开(公告)日：2011-03-08

申请号：US12651150

申请日：2009-12-31

Applicant: James David Britton ,  Jorge Eduardo Martinez-Vargas

Inventor： James David Britton ,  Jorge Eduardo Martinez-Vargas

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/3447 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0352 ,  H05K2201/062 ,  H05K2201/09309 ,  Y10T29/49144

Abstract: Apparatuses and methods that provide for enhanced connections between PTHs of multi-layer PCBs and electronic component leads, pins or the like, are described herein. The apparatuses and methods improve the likelihood that the PTHs are completely filled with solder thereby advantageously allowing the PCBs to exhibit high mechanical and electrical reliability. Complete filling of PTHs is achieved by configuring the electrically conductive layers within the multi-layer PCB stack in a manner that reduces the heat sinking effects of the layers during the soldering process. In this regard, the PTHs may not directly contact all of the internal ground or power planes, so the heat sinking or heat transfer effects are reduced. This feature enables molten solder to substantially or completely fill an entire PTH before freezing.

Abstract translation: 本文描述了提供多层PCB的PTH与电子部件引线，引脚等之间的增强连接的装置和方法。 这些装置和方法提高了PTH完全填充焊料的可能性，从而有利地允许PCB显示出高的机械和电气可靠性。 通过在多层PCB堆叠内配置导电层，以减少焊接过程中各层的散热效应的方法来实现PTH的完全填充。 在这方面，PTH可能不直接接触所有内部地面或电力平面，因此减少了散热或传热效应。 该特征使得熔融焊料在冷冻之前基本上或完全填充整个PTH。