公开(公告)号：US5027062A

公开(公告)日：1991-06-25

申请号：US364876

申请日：1989-06-12

Applicant: William P. Dugan ,  Marvin R. Johnson

Inventor： William P. Dugan ,  Marvin R. Johnson

IPC: G01R1/067 ,  G01R1/073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4007 ,  G01R1/07314 ,  G01R1/06711 ,  G01R3/00 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1476 ,  H05K3/062 ,  H05K3/064 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4647

Abstract: A method for manufacturing a probe test structure for microcircuits utilizes a multiple coating method in conjunction with a novel double-cell electroplating apparatus having a relatively high-resistance ion path between the cells. Photoresist is applied to both sides of a copper foil, copper posts are electroformed onto selected areas of one side of the foil through image hole patterns, the remaining photoresist is stripped away, polyimide prepreg is laminated to the post side of the foil, the copper posts are exposed by sanding, photoresist is reapplied to both sides of the sanded remainder, additional copper is electroformed on each post through image hole patterns in the post side of the photoresist, the foil on the side opposite the posts is chemically milled to provide leads integral with each post using appropriate masking techniques and, finally, all of the remaining photoresist is removed to leave the desired test probe set. In a second embodiment, nickel plating is added over the copper to achieve selective etching, permitting processing of both sides of the copper foil simultaneously.

Abstract translation: 一种用于制造微电路探针测试结构的方法利用多层涂覆方法与新颖的双电池电镀设备相结合，该双电池电镀设备在电池之间具有相对较高的电阻离子路径。 将光刻胶施加到铜箔的两面，铜柱通过图像孔图案电铸成箔的一侧的选定区域，残留的光致抗蚀剂被剥离，聚酰亚胺预浸料层压到箔的后侧，铜 通过砂光曝光柱，将光致抗蚀剂重新施加到磨砂剩余部分的两侧，通过在光致抗蚀剂的后侧中的图像孔图案，在每个柱上电铸附加的铜，将化学铣削在柱的相对侧上的箔以提供引线 使用适当的掩蔽技术与每个柱整体，最后，除去所有剩余的光致抗蚀剂以留下所需的测试探针组。 在第二实施例中，在铜上添加镍电镀以实现选择性蚀刻，从而允许铜箔的两面同时加工。

公开(公告)号：US4878294A

公开(公告)日：1989-11-07

申请号：US208907

申请日：1988-06-20

Applicant: William P. Dugan ,  Marvin R. Johnson

Inventor： William P. Dugan ,  Marvin R. Johnson

IPC: G01R1/067 ,  G01R1/073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4007 ,  G01R1/07314 ,  G01R1/06711 ,  G01R3/00 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1476 ,  H05K3/062 ,  H05K3/064 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4647 ,  Y10T29/49165

Abstract: A method for manufacturing a probe test structure for microcircuits utilizes a multiple coating method in conjunction with a novel double-cell electroplating apparatus having a relatively high-resistance ion path between the cells. Photoresist is applied to both sides of a copper foil, copper posts are electroformed onto selected areas of one side of the foil through image hole patterns, the remaining photoresist is stripped away, polyimide prepreg is laminated to the post side of the foil, the copper posts are exposed by sanding, photoresist is reapplied to both sides of the sanded remainder, additional copper is electroformed on each post through image hole patterns in the post side of the photoresist, the foil on the side opposite the posts is chemically milled to provide leads integral with each post using appropriate masking techniques and, finally, all of the remaining photoresist is removed to leave the desired test probe set. In a second embodiment, nickel plating is added over the copper to acheive selective etching, permitting processing of both sides of the copper foil simultaneously.

Abstract translation: 一种用于制造微电路探针测试结构的方法利用多层涂覆方法与新颖的双电池电镀设备相结合，该双电池电镀设备在电池之间具有相对较高的电阻离子路径。 将光刻胶施加到铜箔的两面，铜柱通过图像孔图案电铸成箔的一侧的选定区域，残留的光致抗蚀剂被剥离，聚酰亚胺预浸料层压到箔的后侧，铜 通过砂光曝光柱，将光致抗蚀剂重新施加到磨砂剩余部分的两侧，通过在光致抗蚀剂的柱侧中的图像孔图案，在每个柱上电铸附加的铜，将化学铣削在柱的相对侧上的箔以提供引线 使用适当的掩蔽技术与每个柱整体，最后，除去所有剩余的光致抗蚀剂以留下所需的测试探针组。 在第二实施例中，通过铜上镀镍以进行选择性蚀刻，从而允许铜箔的两面同时加工。

公开(公告)号：US20170018440A1

公开(公告)日：2017-01-19

申请号：US15282255

申请日：2016-09-30

Applicant: Tessera, Inc.

Inventor： Belgacem Haba ,  Vage Oganesian ,  Kimitaka Endo

IPC: H01L21/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/24226 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/0038 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0382 ,  H05K2201/096 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1189 ,  H01L2924/00

Abstract: An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.

Abstract translation: 互连元件130可以包括具有顶面116b和远离顶面的底面116a的介电层116，限定沿着底面延伸的平面的第一金属层和沿着顶面延伸的第二金属层。 第一或第二金属层之一或两者可以包括多个导电迹线132,134。多个导电突起112可以从由第一金属层102限定的平面向上延伸穿过电介质层116.导电 突起112可以具有在第一金属层132上方的第一高度115处的顶表面126，其可以超过介电层的高度的50％。 多个导电通孔128可以从突起112的顶表面126延伸，以将突起112与第二金属层连接。

公开(公告)号：US08065797B2

公开(公告)日：2011-11-29

申请号：US11896774

申请日：2007-09-05

Applicant: Ryoichi Watanabe ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Joon-Sung Kim ,  Seung-Chul Kim ,  Myung-San Kang

Inventor： Ryoichi Watanabe ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Joon-Sung Kim ,  Seung-Chul Kim ,  Myung-San Kang

IPC: H01K3/10 ,  H05K3/36 ,  H05K3/02 ,  H05K3/10 ,  H05K1/00 ,  H05K1/09

CPC classification number: H05K3/0017 ,  H05K3/0014 ,  H05K3/045 ,  H05K3/06 ,  H05K3/107 ,  H05K3/20 ,  H05K3/205 ,  H05K3/426 ,  H05K3/4614 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/0361 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2203/0278 ,  H05K2203/0384 ,  H05K2203/0582 ,  H05K2203/1152 ,  H05K2203/1189 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of fabricating a printed circuit board is disclosed. A method of fabricating a printed circuit board that includes: stacking an insulation layer on at least one surface of a core layer, on which an inner circuit is formed, and forming an outer circuit pattern; burying the outer circuit pattern in the insulation layer; removing the outer circuit pattern to form minute grooves and curing the insulation layer; and forming an outer circuit by filling metal in the minute grooves, makes it possible to readily form high-resolution fine-line circuits, as well as to reduce fabrication costs and increase productivity.

Abstract translation: 公开了一种制造印刷电路板的方法。 一种制造印刷电路板的方法，包括：在形成有内部电路的芯层的至少一个表面上堆叠绝缘层，并形成外部电路图案; 将外部电路图案埋在绝缘层中; 去除外部电路图案以形成微小凹槽并固化绝缘层; 通过在金属槽中填充金属而形成外部电路，可以容易地形成高分辨率的细线电路，并且能够降低制造成本并提高生产率。

公开(公告)号：US20090188706A1

公开(公告)日：2009-07-30

申请号：US12317707

申请日：2008-12-23

Applicant: Kimitaka Endo

Inventor： Kimitaka Endo

IPC: H05K1/02 ,  H05K1/11 ,  B32B37/02 ,  B44C1/22

CPC classification number: H01R43/0256 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13609 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H05K1/185 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/10674 ,  H05K2203/0384 ,  H05K2203/0542 ,  H01L2224/05599

Abstract: An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.

Abstract translation: 公开了互连元件及其制造方法。 互连元件可以包括多个金属导体，多个固体金属凸块和低熔点（LMP）金属层。 固体金属凸起并且远离相应导体的第一方向突出。 每个凸块具有至少一个沿至少一个横向于第一方向的第二方向限定凸块的边缘。 低熔点（LMP）金属层具有连接到各个导体的第一面，并且通过至少一个边缘和与凸块相连的第二面沿第二方向限定。 凸块和LMP层的边缘在第一方向上对齐，并且LMP金属层的熔化温度基本上低于导体。

公开(公告)号：US20090145630A1

公开(公告)日：2009-06-11

申请号：US11719803

申请日：2005-11-18

Applicant: Mitsuhiro Watanabe ,  Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida ,  Koji Nanbu

Inventor： Mitsuhiro Watanabe ,  Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida ,  Koji Nanbu

IPC: H05K1/09 ,  H05K1/02 ,  B32B37/02

CPC classification number: H05K3/427 ,  H05K1/0265 ,  H05K1/116 ,  H05K3/062 ,  H05K3/20 ,  H05K3/4658 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/1476 ,  Y10T156/10

Abstract: To provide a printed wiring board and a method for manufacturing the printed wiring board in which circuit widths of a signal transmission circuit and a power supply circuit or the like, which conventionally require to have greatly different circuit widths, are close to each other as much as possible and substantial miniaturization can be achieved. In order to achieve this object, a printed wiring board obtained by etching a metal-clad laminate including a conductive layer and an insulating layer is employed, in which a first circuit and a second circuit having different thicknesses formed in a same reference plane coexist. In addition, it is characterized in that a thicker circuit of the first circuit or the second circuit has a clad-like configuration in which three layers of a first copper layer/a different kind of metal layer/a second copper layer are sequentially stacked. Further, a manufacture of the printed wiring board is characterized in that a clad composite material in which three layers of a first copper layer/a different kind of metal layer/a second copper layer are sequentially stacked is a start material, and selective etching characteristic between the different kind of metal layer and the copper layer is effectively utilized.

Abstract translation: 为了提供印刷电路板和制造印刷电路板的方法，其中传统上需要具有大大不同的电路宽度的信号传输电路和电源电路等的电路宽度彼此接近 并且可以实现实质的小型化。 为了实现该目的，采用通过蚀刻包括导电层和绝缘层的覆金属层压板获得的印刷布线板，其中形成在相同参考平面中的具有不同厚度的第一电路和第二电路共存。 此外，其特征在于，第一电路或第二电路的较厚电路具有层叠结构，其中第一铜层/不同种类的金属层/第二铜层三层依次层叠。 此外，印刷布线板的制造的特征在于，其中顺序层叠有三层第一铜层/不同种类的金属层/第二铜层的复合材料是起始材料，并且选择性蚀刻特性 在不同种类的金属层和铜层之间有效地利用。

公开(公告)号：US20090115047A1

公开(公告)日：2009-05-07

申请号：US12287380

申请日：2008-10-08

Applicant: Belgacem Haba ,  Vage Oganesian ,  Kimitaka Endo

Inventor： Belgacem Haba ,  Vage Oganesian ,  Kimitaka Endo

IPC: H01L23/522 ,  B32B38/00 ,  C23F1/00 ,  B32B38/10 ,  H01L21/768

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/24226 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/0038 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0382 ,  H05K2201/096 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1189 ,  H01L2924/00

Abstract: An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.

Abstract translation: 互连元件130可以包括具有顶面116b和远离顶面的底面116a的介电层116，限定沿着底面延伸的平面的第一金属层和沿着顶面延伸的第二金属层。 第一或第二金属层之一或两者可以包括多个导电迹线132,134。多个导电突起112可以从由第一金属层102限定的平面向上延伸穿过电介质层116.导电 突起112可以具有在第一金属层132上方的第一高度115处的顶表面126，其可以超过介电层的高度的50％。 多个导电通孔128可以从突起112的顶表面126延伸，以将突起112与第二金属层连接。

公开(公告)号：US20090002964A1

公开(公告)日：2009-01-01

申请号：US11824484

申请日：2007-06-29

Applicant: Belgacem Haba

Inventor： Belgacem Haba

IPC: H01R9/00

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2203/0384 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming contacts for an interconnection element, includes (a) joining a conductive element to an interconnection element having multiple wiring layers, (b) patterning the conductive element to form conductive pins, and (c) electrically interconnecting the conductive pins with conductive features of the interconnection element. A multiple wiring layer interconnection element having an exposed pin interface, includes an interconnection element having multiple wiring layers separated by at least one dielectric layer, the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element, a plurality of conductive pins protruding in a direction away from the first face, and metal features electrically interconnecting the conductive features with the conductive pins.

公开(公告)号：US07451540B2

公开(公告)日：2008-11-18

申请号：US11552368

申请日：2006-10-24

Applicant: Jaroslaw A. Magera ,  Gregory J. Dunn ,  Jovica Savic

Inventor： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Jovica Savic

IPC: H05K3/02 ,  B05D5/12

CPC classification number: H05K3/20 ,  H05K1/167 ,  H05K3/06 ,  H05K3/205 ,  H05K3/244 ,  H05K2201/0361 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Fabricating (100, 1300) a printed circuit board includes fabricating patterned conductive traces (305, 310, 1410, 1415) onto a foil, laminating the patterned conductive traces to a printed circuit board substrate (405, 1505) by pressing on the foil, such that the conductive traces are pressed into a dielectric layer of the printed circuit board, and removing the foil to expose a co-planar surface of conductive trace surfaces and dielectric surfaces. Removal may be done by peeling (125) and/or etching (130, 1315).

Abstract translation: 制造（100,1300）印刷电路板包括在箔上制造图案化的导电迹线（305,310,1410,1415），通过压在箔上将图案化的导电迹线层压到印刷电路板衬底（405,1505）上， 使得导电迹线被压入印刷电路板的电介质层，并且去除箔以暴露导电迹线表面和电介质表面的共面表面。 可以通过剥离（125）和/或蚀刻（130,1315）进行去除。

公开(公告)号：US07441330B2

公开(公告)日：2008-10-28

申请号：US11581589

申请日：2006-10-17

Applicant: Kenji Takano ,  Munekazu Shibata ,  Kazuya Arai ,  Junichi Kanai ,  Kaoru Sugimoto

Inventor： Kenji Takano ,  Munekazu Shibata ,  Kazuya Arai ,  Junichi Kanai ,  Kaoru Sugimoto

IPC: H05K3/02

CPC classification number: H05K3/20 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for producing a circuit board includes the steps of etching the third metal layer of a three-layer metal laminate into a predetermined interconnection pattern by photolithography; forming a laminate on the interconnection pattern by a buildup method, the laminate including interconnection patterns with insulating layers provided therebetween, the interconnection patterns being electrically connected to each other; separating a first metal layer from a supporting substrate to detach the laminate; removing the first metal layer of the three-layer metal laminate by etching using a second metal layer as a barrier layer; and removing the exposed second metal layer by etching.

Abstract translation: 制造电路板的方法包括以下步骤：通过光刻将三层金属层压体的第三金属层蚀刻成预定的互连图案; 通过积层法在所述互连图案上形成层压体，所述层压体包括布置在其间的绝缘层的互连图案，所述互连图案彼此电连接; 从支撑基板分离第一金属层以分离层压体; 通过使用第二金属层作为阻挡层进行蚀刻来去除三层金属层叠体的第一金属层; 并通过蚀刻去除暴露的第二金属层。