公开(公告)号：US20090170348A1

公开(公告)日：2009-07-02

申请号：US12023008

申请日：2008-01-30

Applicant: YI RUI ,  AI-YU PAN ,  JIAN-SHE SHEN ,  MEI HUANG

Inventor： YI RUI ,  AI-YU PAN ,  JIAN-SHE SHEN ,  MEI HUANG

IPC: H02B1/056

CPC classification number: G06F13/4068 ,  G06F2213/0026 ,  H05K1/0237 ,  H05K1/0295 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/09227 ,  H05K2201/09954 ,  H05K2201/10189

Abstract: An exemplary patch panel includes a printed circuit board having a plurality of signal terminals for connecting to two pairs of peripheral component interconnect express (PCI-E) X1 differential signal terminals of an I/O controller hub (ICH), an interface terminal of a high definition multimedia interface (HDMI), four pairs of differential signal terminals of the HDMI, four pairs of differential signal terminals of a graphic and memory controller hub (GMCH), one of another differential signal terminal of the GMCH, and two pairs of differential signal terminals of a PCI-E X16 slot. Therefore, the ICH is connected to the PCI-E X16 slot via the patch panel for supporting a PCI-E X1 card while the GMCH is connected to the HDMI via the patch panel. A patch panel connector is provided to mount the patch panel on a motherboard.

Abstract translation: 示例性接线板包括具有多个信号端子用于连接到I / O控制器集线器（ICH）的两对外围组件互连快速（PCI-E）X1差分信号端子的印刷电路板， 高分辨率多媒体接口（HDMI），HDMI对的四对差分信号端子，图形和存储器控制器集线器（GMCH）的四对差分信号端子，GMCH的另一个差分信号端子和两对差分 PCI-E X16插槽的信号端子。 因此，ICH通过接线板连接到PCI-E X16插槽，用于支持PCI-E X1卡，而GMCH通过接线板连接到HDMI。 提供了一个接线板连接器，用于将接线板安装在主板上。

公开(公告)号：US20090147492A1

公开(公告)日：2009-06-11

申请号：US12330410

申请日：2008-12-08

Applicant: Hans-Jurgen Heinrichs ,  Melanie Sell

Inventor： Hans-Jurgen Heinrichs ,  Melanie Sell

IPC: H05K1/14

CPC classification number: G06F1/185 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/10189

Abstract: The invention relates to a data processing system with a main board, in which main board has at least one multipoint connector, in which at least one riser card is accommodated, and a first daughter card is accommodated in first riser card in such a manner that first daughter card is arranged parallel to main board. The data processing system further comprises a second multipoint connector, wherein a second riser card is accommodated in second multipoint connector, and a second daughter card is accommodated in second riser card in such a manner that second daughter card is arranged parallel to main board. The First multipoint connector and the second multipoint connectors are arranged on opposite outer sides of the main board. Each daughter card comprises a respective I/O interface which each cooperates with a common rear panel and is pointed towards the common rear panel. Relative to second daughter card, first daughter card is arranged rotated by 180° about an axis running parallel to main board.

Abstract translation: 本发明涉及一种具有主板的数据处理系统，其中主板具有至少一个多点连接器，其中容纳至少一个转接卡，并且第一子卡被容纳在第一转接卡中，使得 第一个子卡与主板平行排列。 数据处理系统还包括第二多点连接器，其中第二转接卡被容纳在第二多点连接器中，并且第二子卡被容纳在第二转接卡中，使得第二子卡平行于主板布置。 第一多点连接器和第二多点连接器布置在主板的相对的外侧上。 每个子卡包括各自的I / O接口，每个I / O接口与公共后面板协作并且指向公共后面板。 相对于第二子卡，第一子卡围绕平行于主板的轴线旋转180°。

公开(公告)号：US20090146759A1

公开(公告)日：2009-06-11

申请号：US11965744

申请日：2007-12-28

Applicant: SHOU-KUO HSU ,  HSIAO-CHUAN TU ,  YU-CHANG PAI

Inventor： SHOU-KUO HSU ,  HSIAO-CHUAN TU ,  YU-CHANG PAI

IPC: H01P5/12

CPC classification number: H01P5/12 ,  H05K1/0246 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022

Abstract: A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal via a main transmission line, a second node coupled to the first node via a first branch transmission line, a first receiving terminal coupled to the first node via a second branch transmission line, a third node coupled to the second node via a third branch transmission line, and a second receiving terminal coupled to the second node via a fourth branch transmission line. The second branch transmission line is longer than the first transmission line, and a first resistor is connected in the second branch transmission line. The third branch transmission line is longer than the fourth branch transmission line, and a second resistor is connected in the third branch transmission line.

Abstract translation: 用于多个负载的电路拓扑包括驱动终端，经由主传输线耦合到驱动终端的第一节点，经由第一分支传输线耦合到第一节点的第二节点，经由第一节点经由 第二分支传输线，经由第三分支传输线耦合到第二节点的第三节点，以及经由第四分支传输线耦合到第二节点的第二接收终端。 第二分支传输线比第一传输线长，并且第一电阻器连接在第二分支传输线路中。 第三分支传输线比第四分支传输线长，并且第二电阻器连接在第三分支传输线路中。

公开(公告)号：US07544096B2

公开(公告)日：2009-06-09

申请号：US11902552

申请日：2007-09-24

Applicant: Thomas S. Cohen ,  Mark W. Gallus ,  John R. Dunham

Inventor： Thomas S. Cohen ,  Mark W. Gallus ,  John R. Dunham

IPC: H01R13/648

CPC classification number: H01R12/716 ,  H01R12/585 ,  H01R12/724 ,  H01R12/727 ,  H01R13/514 ,  H01R13/6474 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/14 ,  H05K7/1445 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A differential connector has a plurality of rows. Each row includes a plurality of signal conductors provided as differential pairs. Each signal conductor has a first contact end connectable to a printed circuit board, a second contact end, and an intermediate portion having a first width. For each differential pair, one first contact end lies along a first line parallel to the plurality of rows and the other first contact end lies along a second line parallel to and spaced from the first line. The differential connector further includes a plurality of ground conductors, with each ground conductor corresponding to a differential pair. Each ground conductor has a first contact end connectable to the printed circuit board, a second contact end, and an intermediate portion having a second width that is at least twice the first width.

Abstract translation: 差分连接器具有多行。 每行包括多个作为差分对提供的信号导体。 每个信号导体具有可连接到印刷电路板的第一接触端，第二接触端和具有第一宽度的中间部分。 对于每个差分对，一个第一接触端沿着平行于多个行的第一线设置，而另一个第一接触端沿着与第一线平行并与其隔开的第二线。 差分连接器还包括多个接地导体，每个接地导体对应于差分对。 每个接地导体具有可连接到印刷电路板的第一接触端，第二接触端和具有至少两倍于第一宽度的第二宽度的中间部分。

公开(公告)号：US20090140755A1

公开(公告)日：2009-06-04

申请号：US11998607

申请日：2007-11-30

Applicant: Charles Calvin Byers ,  Thomas B. Cook ,  Bradford Gene Van Treuren

Inventor： Charles Calvin Byers ,  Thomas B. Cook ,  Bradford Gene Van Treuren

IPC: G01R31/304

CPC classification number: H05K1/14 ,  H04B10/803 ,  H05K2201/044 ,  H05K2201/10121

Abstract: System including backplane, and first and second circuit boards. First circuit board is attached to backplane and has first optical signal transmitter. Second circuit board is attached to backplane and has first optical signal receiver. First optical signal transmitter and first optical signal receiver are mutually configured and mutually aligned for circuit board test signal communication from first circuit board to second circuit board across free space. Method includes providing backplane and first and second circuit boards, where first circuit board has first optical signal transmitter and second circuit board has first optical signal receiver. Method further includes attaching first and second circuit boards to backplane, and mutually configuring and mutually aligning first optical signal transmitter and first optical signal receiver for circuit board test signal communication from first circuit board to second circuit board across free space.

Abstract translation: 系统包括背板，第一和第二电路板。 第一个电路板连接到背板，并具有第一个光信号发射器。 第二电路板连接到背板，并具有第一个光信号接收器。 第一光信号发射器和第一光信号接收器相互配置并相互对准用于跨越自由空间的第一电路板到第二电路板的电路板测试信号通信。 方法包括提供背板和第一和第二电路板，其中第一电路板具有第一光信号发射器，第二电路板具有第一光信号接收器。 方法还包括将第一和第二电路板连接到背板，并且将第一光信号发射器和第一光信号接收器相互配置和相互对准，用于跨越自由空间的第一电路板到第二电路板的电路板测试信号通信。

公开(公告)号：US07523244B2

公开(公告)日：2009-04-21

申请号：US11459858

申请日：2006-07-25

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/42

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory module includes a first signal line to carry a first signal that enters the module at a first end of the first signal line and a second signal line to carry a second signal that enters the module at a first end of the second signal line. The module includes a first memory device disposed on a first side of the module and a second memory module disposed on a second side of the module positioned opposite to the first side. The first memory device and the second memory device are connected to the first signal line and the second signal line. The first signal and the second signal traverse alongside each other to arrive in turn at the first memory device and the second memory device.

Abstract translation: 存储器模块包括：第一信号线，用于承载在第一信号线的第一端进入模块的第一信号;以及第二信号线，用于承载在第二信号线的第一端进入模块的第二信号。 模块包括设置在模块的第一侧上的第一存储器件和设置在与第一侧相对定位的模块的第二侧上的第二存储器模块。 第一存储器件和第二存储器件连接到第一信号线和第二信号线。 第一信号和第二信号彼此并行地依次移动以在第一存储器件和第二存储器件上依次进入。

公开(公告)号：US20090086561A1

公开(公告)日：2009-04-02

申请号：US11952140

申请日：2007-12-07

Applicant: SHOU-KUO HSU ,  DUEN-YI HO ,  CHENG-SHIEN LI

Inventor： SHOU-KUO HSU ,  DUEN-YI HO ,  CHENG-SHIEN LI

IPC: G11C5/14 ,  H05K1/11

CPC classification number: G06F1/26 ,  G11C5/04 ,  G11C5/147 ,  H05K1/0262 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10159

Abstract: An exemplary motherboard includes a driving module, a first slot module arranged for mounting a first type of memory and connected to the driving module via a first channel, a second slot module arranged for mounting a second type of memory and connected to the driving module via a second channel, and a voltage regulator electronically connected to the first slot module and the second slot module. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.

Abstract translation: 示例性主板包括驱动模块，布置成用于安装第一类型存储器并经由第一通道连接到驱动模块的第一插槽模块，布置成用于安装第二类型存储器并连接到驱动模块的第二插槽模块，其经由 第二通道和电连接到第一插槽模块和第二插槽模块的电压调节器。 第一存储器和第二存储器替代地安装在母板上，电压调节器检测当前安装在母板上的哪种类型的存储器，并相应地输出适合安装在母板上的存储器类型的电压。

公开(公告)号：US20090045889A1

公开(公告)日：2009-02-19

申请号：US11891785

申请日：2007-08-13

Applicant: Joel R. Goergen ,  Greg Hunt

Inventor： Joel R. Goergen ,  Greg Hunt

IPC: H03H7/01 ,  H01K3/00 ,  H05K1/11

CPC classification number: H05K3/429 ,  H05K1/0216 ,  H05K1/0237 ,  H05K3/0047 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09845 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/175 ,  Y10T29/49165

Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru-holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.

Abstract translation: 公开了一种高速路由器背板。 路由器背板在多个信号层上使用差分信号对，每个信号对夹在一对数字接地层之间。 通孔用于将差分信号对连接到外部组件。 为了降低路由复杂度，差分信号对中的至少一些在其路径的某处沿着不同的信号层路由通路对。 钻出至少一些通孔和通孔以减少孔的导电短截线长度部分。 孔的钻孔部分包括从第一轮廓到第二轮廓的转变，以减少从钻孔的端部的射频反射。

公开(公告)号：US07492605B2

公开(公告)日：2009-02-17

申请号：US11473359

申请日：2006-06-22

Applicant: Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

Inventor： Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

IPC: H05K1/11 ,  H05K1/00

CPC classification number: H05K1/0265 ,  H05K1/0254 ,  H05K2201/044 ,  H05K2201/0784 ,  H05K2201/093 ,  H05K2201/0969

Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.

Abstract translation: 包括供电电源插座，第一连接器电源插座和第二电源插座的电力平面，其中电源电极插座和第一连接器电源插座之间的第一电阻基本上等于第二电阻 在电源插座和第二连接器电源插座之间。

公开(公告)号：US20080285248A1

公开(公告)日：2008-11-20

申请号：US12011298

申请日：2008-01-25

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/18

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09781

Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. Specific via designs reduce differential signal distortion due to the via pair, allowing the backplane to operate reliably at differential signal rates in excess of 3 Gigabits per second. In particular, each via passes through nonfunctional conductive pads on selected digital ground plane layers, the pads separated from the remainder of its ground plane layer by a clearance, thereby modifying the impedance of the via and reducing reflections from the stubs created by the via.