公开(公告)号：US07269813B2

公开(公告)日：2007-09-11

申请号：US10991360

申请日：2004-11-19

Applicant: Paul Brown

Inventor： Paul Brown

IPC: G06F17/50 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Enlarged spacing is provided between rows of vias in a ball grid array (BGA) multilayered printed wiring board land pattern in which the lands in the pattern are connected to the vias by a link connector by rotating, elongating, and/or truncating selected consecutive link connectors and rotating their respective corresponding vias in a row or column or selected consecutive rows or columns to achieve the enlarged spacing between rows or columns of vias in the BGA land pattern. Enhanced spacing between selected grid columns or rows of vias is provided such that some of the grid pitches for the vias are equal to that of the standard BGA and at least some are of a greater grid pitch.

Abstract translation: 在球栅阵列（BGA）多层印刷布线板焊盘图案中的通孔列之间设置放大的间隔，其中图案中的焊盘通过链接连接器通过旋转，延长和/或截断选定的连续链接 连接器，并且将它们各自的对应的通孔以行或列或所选的连续的行或列旋转，以实现BGA焊盘图案中的通孔的行或列间的间隔。 提供所选网格列或通孔列之间的增强间距，使得用于通孔的一些网格间距等于标准BGA的网格间距，并且至少一些具有更大的网格间距。

公开(公告)号：US20070102817A1

公开(公告)日：2007-05-10

申请号：US11616164

申请日：2006-12-26

Applicant: Cheng Tay ,  Swee Cheng ,  Eng Goh

Inventor： Cheng Tay ,  Swee Cheng ,  Eng Goh

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.

Abstract translation: 提供了一种方法和装置，其涉及抵抗在球栅阵列微电子封装中的部件和基板之间的电互连中的裂纹起始和传播。 电介质限定和非介质限定的电互连的混合物减少了电互连故障的可能性，而不必控制介质限定的衬底互连比。 此外，电互连的电介质限定边缘部分远离开始点的选择性取向抵抗裂纹扩展和部件故障。

公开(公告)号：US20070091704A1

公开(公告)日：2007-04-26

申请号：US11437846

申请日：2006-05-19

Applicant: Siva RaghuRam ,  Josef Schuster ,  Simon Muff ,  Abdallah Bacha

Inventor： Siva RaghuRam ,  Josef Schuster ,  Simon Muff ,  Abdallah Bacha

IPC: G11C7/00

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/063 ,  H05K2201/09409 ,  H05K2201/09418 ,  Y02P70/611

Abstract: In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type that are mounted on at least one outer face of the printed circuit board. The printed circuit board has a connector strip, which runs at a first edge of the at least one outer face in a first direction and has a multiplicity of electrical contacts that are lined up in the first direction. The printed circuit board extends in the first direction between two opposite second edges. At least nine of the semiconductor chips of the same type are respectively mounted next to one another on the outer face of the printed circuit board between the center of the printed circuit board and the respective second edge of the printed circuit board. The semiconductor chips of the same type respectively have a smaller dimension and, in the direction perpendicular to the smaller dimension, a larger dimension that is larger than the smaller dimension. A respective first group of four of the semiconductor chips of the same type, which are oriented so as to have their shorter dimension parallel to the connector strip, is arranged at the respective second edge of the printed circuit board. A second group of five semiconductor chips of the same type is respectively arranged between the first group of semiconductor chips and the center of the printed circuit board. The first group of semiconductor chips and the second group of semiconductor chips are actuated by two separate line buses whose conductor tracks branch toward all the semiconductor chips in the respective group of semiconductor chips.

Abstract translation: 在第一实施例中，本发明提供一种具有电子印刷电路板和安装在印刷电路板的至少一个外表面上的相同类型的多个半导体芯片的存储模块。 印刷电路板具有一个连接器条，其在第一方向的至少一个外表面的第一边缘处延伸，并且具有在第一方向上排列的多个电触点。 印刷电路板沿第一方向在两个相对的第二边缘之间延伸。 在印刷电路板的中心和印刷电路板的相应第二边缘之间，相同类型的至少九个半导体芯片分别彼此相邻地安装在印刷电路板的外表面上。 相同类型的半导体芯片分别具有较小的尺寸，并且在垂直于较小尺寸的方向上具有大于较小尺寸的较大尺寸。 在印刷电路板的相应第二边缘处布置相同类型的四个半导体芯片的相应的第一组，其被定向成具有与连接器条平行的较短尺寸。 第一组相同类型的五个半导体芯片分别布置在第一组半导体芯片和印刷电路板的中心之间。 第一组半导体芯片和第二组半导体芯片由两条单独的线路总线驱动，其导体轨迹分支到相应的半导体芯片组中的所有半导体芯片。

公开(公告)号：US07167936B2

公开(公告)日：2007-01-23

申请号：US10348421

申请日：2003-01-21

Applicant: Paul Lindt

Inventor： Paul Lindt

IPC: G06F3/00 ,  H01P3/00 ,  H01P3/08 ,  G11C5/02 ,  H01L21/44

CPC classification number: H05K1/0248 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/09418 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Circuit board having a plurality of bus lines (6), which run on the circuit board (1) essentially parallel to a preferred direction of the circuit board (1), and having at least one integrated circuit (3) for the high-speed data processing of data, which integrated circuit is arranged on the circuit board (1), is integrated in a housing (4) having a plurality of housing sides (5) and has a plurality of parallel interfaces for connection to the bus lines (6), in which case the housing sides (5) of the integrated circuits (3) are oriented at an inclination with respect to the preferred direction of the circuit board (2).

Abstract translation: 具有多个总线（6）的电路板，其基本上平行于电路板（1）的优选方向在电路板（1）上延伸，并且具有用于高速的至少一个集成电路（3） 该集成电路布置在电路板（1）上的数据的数据处理集成在具有多个壳体侧面（5）的壳体（4）中，并且具有用于连接到总线（6）的多个并行接口 ），在这种情况下，集成电路（3）的壳体侧（5）相对于电路板（2）的优选方向倾斜。

公开(公告)号：US07102721B2

公开(公告)日：2006-09-05

申请号：US10939383

申请日：2004-09-14

Applicant: Hiroshi Ueda ,  Hitoshi Morishita

Inventor： Hiroshi Ueda ,  Hitoshi Morishita

IPC: G02F1/1345

CPC classification number: H05K3/361 ,  G02F1/1345 ,  H05K1/117 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427

Abstract: The present invention is directed to a liquid crystal display including: a plurality of electrode terminals arranged on one of end faces of a TFT glass substrate in such a manner as to be aligned on an imaginary line; and a plurality of lead terminals of a tape carrier package aligned on the electrode terminals, said plurality of lead terminals connected through an anisotropic conductive film; wherein the electrode terminals near the end face of the glass substrate is formed obliquely in such a manner as to be extended in the direction of both right and left with respect to the plurality of electrode terminals.

Abstract translation: 本发明涉及一种液晶显示器，它包括：多个电极端子，以在假想线上对齐的方式设置在TFT玻璃基板的一个端面上; 以及在所述电极端子上排列的带状载体封装体的多个引线端子，所述多个引线端子通过各向异性导电膜连接; 其中靠近玻璃基板的端面的电极端子以相对于多个电极端子在左右两个方向上延伸的方式倾斜地形成。

公开(公告)号：US20060094222A1

公开(公告)日：2006-05-04

申请号：US10977157

申请日：2004-10-29

Applicant: Chee Wong ,  Chee Lee

Inventor： Chee Wong ,  Chee Lee

IPC: H01L21/44

CPC classification number: H01L23/5286 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/10719 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.

Abstract translation: 集成电路管芯端子布置和配置，用于将集成电路管芯安装在封装衬底上，以减少封装传输路径。 在一个实施例中，对于在管芯外部的迹线长度敏感的信号的端子设置在管芯的角部。 模具相对于封装衬底以一定角度安装在封装衬底上，以将芯片的角部指向封装衬底的边缘，以减小管芯外部的迹线长度。 管芯的中心可以与衬底的中心重合或者不一致。 在一个实施例中，当与居中的未旋转的模具安装位置相比时，安装具有指向封装基板边缘的拐角的模具不会引起基板翘曲的显着差异。

公开(公告)号：US20050040502A1

公开(公告)日：2005-02-24

申请号：US10937647

申请日：2004-09-08

Applicant: Gabe Cherian

Inventor： Gabe Cherian

IPC: H01L23/495 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/12 ,  H01L23/49555 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3426 ,  H05K2201/09418 ,  H05K2201/10318 ,  H05K2201/10386 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10825 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2924/00

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices. The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general. For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with. For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

公开(公告)号：US20040251544A1

公开(公告)日：2004-12-16

申请号：US10847409

申请日：2004-05-17

Applicant: Nokia Corporation

Inventor： Esa Hussa

IPC: H01L023/48

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered comers. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.

Abstract translation: 互连图案设计，在机械冲击和热循环负载下具有改进的可靠性。 半导体部件包括被排列成行和列以形成互连图案的多个互连，其中互连对准，使得图案具有大致圆形或倒角。 本发明提供了改进的球栅阵列封装的互连寿命和可靠性，并且易于实现。

公开(公告)号：US20040104475A1

公开(公告)日：2004-06-03

申请号：US10605660

申请日：2003-10-16

Inventor： Sung-Fei Wang

IPC: H01L023/52

CPC classification number: H05K1/181 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K2201/09418 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

Abstract: A high density semiconductor package comprises a substrate, a first package module and a plurality of second package modules. The substrate has a surface on which the first package module and the second package modules are disposed, wherein the second package modules surround the first package module.

Abstract translation: 高密度半导体封装包括衬底，第一封装模块和多个第二封装模块。 衬底具有其上设置有第一封装模块和第二封装模块的表面，其中第二封装模块围绕第一封装模块。

公开(公告)号：US06670706B2

公开(公告)日：2003-12-30

申请号：US09536148

申请日：2000-03-28

Applicant: Gorou Ikegami

Inventor： Gorou Ikegami

IPC: H01L2940

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/13144 ,  H01L2224/16238 ,  H01L2224/75 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/15787 ,  H05K3/328 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/10674 ,  H05K2203/0285 ,  Y02P70/611 ,  H01L2924/00

Abstract: Parts of pad electrodes formed on an interconnection board so as to correspond to bump electrodes of a semiconductor pellet that neighbor parts superposed with the bump electrodes are caused to extend in substantially the same direction, and ultrasonic vibration is applied in this extension direction so as to make a connection between the pad electrodes and the bump electrodes.

Abstract translation: 形成在互连板上的焊盘电极的部分相对应于与凸起电极重叠的相邻部分的半导体芯片的凸块电极相互延伸大致相同的方向，并且在该延伸方向上施加超声波振动，以便 在焊盘电极和凸块电极之间形成连接。