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公开(公告)号：US12127345B2
公开(公告)日：2024-10-22
申请号：US17779572
申请日：2021-06-11
Inventor： Xiaoxia Huang , Fan Li
CPC classification number: H05K1/147 , H05K1/115 , H05K9/0073 , H05K2201/09545 , H05K2201/10128
Abstract: The present disclosure relates to a display apparatus and an electronic device, relating to the technical field of display. The display apparatus may comprise a display panel, a main circuit board, a bridging circuit board, and a first shielding adhesive tape. The main circuit board may be provided on the back surface of the display panel; the bridging circuit board may be provided at the side of the main circuit board distant from the display panel, and may be connected to the main circuit board in a binding mode; and the first shielding adhesive tape may be provided at the side of the main circuit board distant from the display panel, and expose the bridging circuit board.
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公开(公告)号：US12114419B2
公开(公告)日：2024-10-08
申请号：US17713347
申请日：2022-04-05
Applicant: Dell Products L.P.
Inventor： William Andrew Smith , Mallikarjun Vasa , Bhyrav M. Mutnury
CPC classification number: H05K1/0218 , H05K1/115 , H05K3/42 , H05K2201/09518 , H05K2201/09545
Abstract: An information handling system includes a printed circuit board, a surface mount connector including first and second surface mount connector portions, first and second different pairs, and a ground plane. The first and second surface mount connector portions are mounted on the printed circuit board. The first differential pair is located on the first surface mount connector portion, and the second differential pair is located on the second surface mount connector portion. The ground plane is located in between the first and second surface mount connector portions within the printed circuit board. The first ground via is in physical communication with the ground plane and a first ground pad on a surface of the printed circuit board. The second ground via is in physical communication with the ground plane and a second ground pad on the surface of the printed circuit board.
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公开(公告)号：US20240334601A1
公开(公告)日：2024-10-03
申请号：US18242843
申请日：2023-09-06
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Sangho Jeong , Jongeun Park , Yongduk Lee , Kihwan Kim , Changhwa Park
CPC classification number: H05K1/115 , H05K1/0298 , H05K3/429 , H05K2201/09545 , H05K2201/09827
Abstract: A circuit board includes a first insulation layer, a circuit wire positioned on the first insulation layer, a second insulation layer covering the circuit wire and overlapping a portion of the circuit wire, and having a via hole including a first side wall and a second side wall having different tilt angles and extending in the thickness direction of the first insulation layer, a first seed layer covering the first side wall and the second side wall of the via hole, a second seed layer positioned in the via hole and covering the first seed layer, a third seed layer positioned on an upper surface of the second insulation layer and including the same material as the second seed layer, a first conductive layer positioned on the second seed layer, and a second conductive layer positioned on the third seed layer.
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公开(公告)号：US12052830B2
公开(公告)日：2024-07-30
申请号：US17542867
申请日：2021-12-06
Applicant: R&D Circuits
Inventor： Donald Eric Thompson
CPC classification number: H05K3/426 , C25D3/38 , C25D5/02 , C25D7/00 , H05K1/0222 , H05K1/182 , H05K3/0047 , H05K3/368 , H05K2201/09072 , H05K2201/09545 , H05K2201/10303 , H05K2201/10325 , H05K2201/10409 , H05K2203/0723
Abstract: The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.
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公开(公告)号：US12035477B2
公开(公告)日：2024-07-09
申请号：US17910151
申请日：2021-03-08
Applicant: Rogers Germany GmbH
Inventor： Andreas Meyer , Karsten Schmidt , Tilo Welker
CPC classification number: H05K1/181 , H05K1/0306 , H05K1/183 , H05K3/429 , H05K2201/09036 , H05K2201/09545 , H05K2201/10666 , H05K2203/049
Abstract: An electronics module (100), especially a power electronics module, comprising
a metal-ceramic substrate (1) serving as a carrier and having a ceramic element (10) and a primary component metallization (21),
an insulation layer (40) directly or indirectly connected to the primary component metallization (21), and
a secondary component metallization (22) which is connected to the side of the insulation layer (40) facing away from the metal-ceramic substrate (1) and is especially isolated from the primary component metallization (21) using the insulation layer (40),
wherein the ceramic element (10) has a first size (L1, D1) and the insulation layer (40) has a second size (L2, D2) and a ratio of the second size (L2, D2) to the first size (L1, D1) has a value smaller than 0.8, to form an island-like insulation layer (40) on the primary component metallization (21).-
Patent Agency Ranking
公开(公告)号：US20240098898A1
公开(公告)日：2024-03-21
申请号：US17949732
申请日：2022-09-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Melvin Kent Benedict , Chi Kim Sides , Paul Danna , Michael Chan
CPC classification number: H05K1/115 , H05K3/4038 , H05K2201/09545 , H05K2203/0207
Abstract: One aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer positioned between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to components mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.
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公开(公告)号：US11895772B2
公开(公告)日：2024-02-06
申请号：US17377280
申请日：2021-07-15
Applicant: Unimicron Technology Corp.
Inventor： Chi-Min Chang , Ching-Sheng Chen , Jun-Rui Huang , Wei-Yu Liao , Yi-Pin Lin
CPC classification number: H05K1/115 , H05K1/181 , H05K3/423 , H05K2201/09545
Abstract: An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.
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公开(公告)号：US20240040686A1
公开(公告)日：2024-02-01
申请号：US18227287
申请日：2023-07-27
Applicant: Rolls-Royce Deutschland Ltd & Co KG
Inventor： Maria BØE , Jan Magnus FARSTAD
CPC classification number: H05K1/0203 , H05K1/183 , H05K2201/09545
Abstract: A printed circuit board assembly includes a printed circuit board and a power connector. The printed circuit board includes an upper surface, a lower surface, and plated through-holes. The power connector is arranged at the upper surface of the printed circuit board and includes a plurality of pins extending through the plated through-holes. The plurality of pins are configured to extend through the plated through-holes and protrude from the lower surface of the printed circuit board. A heat spreading block located at the lower surface is provided. Ends of the plurality of pins are arranged in the heat spreading block.
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49.发明公开公开(公告)号：US20240032204A1
公开(公告)日：2024-01-25
申请号：US17952015
申请日：2022-09-23
Applicant: Tong Hsing Electronic Industries, Ltd.
Inventor： Yueh-Kai TANG , Chia-Shuai CHANG , Ming-Yen PAN , Jian-Yu SHIH , Jhih-Wei LAI , Shih-Han WU
CPC classification number: H05K3/06 , H05K3/423 , H05K1/0353 , H05K2203/0723 , H05K2203/107 , H05K2203/1377 , H05K2201/09545
Abstract: A method for manufacturing a conductive circuit board includes the steps of: (a) preparing a substrate having opposite upper and lower surfaces, and at least one through hole extending through the upper and lower surfaces and defined by an inner surface; (b) forming a metal base layer on at least one of the upper and lower surfaces and on the inner surface; (c) etching the metal base layer by a laser beam so that the at least one of the upper and lower surfaces and the inner surface are formed with a patterned metal base layer; and (d) forming a metal circuit layer on the at least one of the upper and lower surfaces and on the inner surface to increase a thickness of the patterned metal base layer. A conductive circuit board manufactured therefrom is also enclosed.
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公开(公告)号：US20230354503A1
公开(公告)日：2023-11-02
申请号：US18344652
申请日：2023-06-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jiun-Yi WU , Chien-Hsun LEE , Chewn-Pu JOU , Fu-Lung HSUEH
IPC: H05K1/02 , H01L21/768 , H01L21/48 , H01L23/498 , H01L23/552 , H05K1/11 , H05K3/00 , H05K3/40 , H05K3/42
CPC classification number: H05K1/0216 , H05K1/024 , H01L21/76805 , H05K1/0222 , H01L21/485 , H01L21/486 , H01L23/49827 , H01L23/552 , H05K1/113 , H05K1/115 , H05K3/0047 , H05K3/4007 , H05K3/423 , H05K1/0245 , H05K3/42 , H05K2201/0959 , Y10T29/49165 , H05K3/4038 , H05K2201/0723 , H05K2201/09545 , H05K2201/09645
Abstract: An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.
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