公开(公告)号：US07964800B2

公开(公告)日：2011-06-21

申请号：US11752843

申请日：2007-05-23

Applicant: Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

Inventor： Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

IPC: H05K1/03

CPC classification number: H05K3/363 ,  H01L2924/0002 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.

Abstract translation: 一种电路板互连结构，具有第一印刷线路板，其中第一导电电路布置在第一绝缘层上，所述第一导电电路在其端部上具有第一连接端子，其中上表面宽度窄于 底面宽度; 第二印刷线路板，其中具有第二连接端子的第二导电层布置在第二绝缘层上; 以及连接层，其沿着所述第一连接端子的纵向侧表面形成圆角，并且将所述第一连接端子和所述第二连接端子互连。 第一连接端子可以具有突出部分。

公开(公告)号：US20110084612A1

公开(公告)日：2011-04-14

申请号：US12707641

申请日：2010-02-17

Applicant: William R. Ratcliffe ,  Jianbiao Pan

Inventor： William R. Ratcliffe ,  Jianbiao Pan

IPC: H01L33/64 ,  H01L33/58 ,  H01L33/00 ,  H01L33/62 ,  H05B37/00

CPC classification number: H01L33/642 ,  F21K9/20 ,  F21K9/23 ,  F21K9/27 ,  F21S4/10 ,  F21V5/04 ,  F21V29/70 ,  F21V29/74 ,  F21V29/89 ,  F21W2131/103 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L25/167 ,  H01L33/62 ,  H01L2224/48137 ,  H05K1/0203 ,  H05K3/0061 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2203/049 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A hybrid chip-on-heatsink device comprises at least one LED die, at least one printed circuit board (PCB), and a thermally conductive substrate or heatsink. The LED die is physically and thermally coupled to the thermally conductive substrate. The PCB is physically coupled to the thermally conductive substrate. The LED die is electrically coupled to the PCB. The thermally conductive substrate acts as a spreader and as a heatsink, whereby heat is efficiently dissipated away from the LED die. The PCB may optionally contain other electrical components, and circuitry to create a “smart” LED package or light engine.

Abstract translation: 混合散热片芯片包括至少一个LED管芯，至少一个印刷电路板（PCB）和导热衬底或散热器。 LED管芯物理和热耦合到导热基板。 PCB物理耦合到导热基板。 LED管芯电连接到PCB。 导热基板用作扩展器和作为散热器，由此将热量有效地从LED管芯中散出。 PCB可以可选地包含其它电气部件和用于创建“智能”LED封装或光引擎的电路。

公开(公告)号：US07888604B2

公开(公告)日：2011-02-15

申请号：US11910685

申请日：2006-04-11

Applicant: Kohichiro Kawate ,  Andrew C. Lottes ,  James G. Vana, Jr. ,  Barbara L. Birrell ,  Alexander W. Barr

Inventor： Kohichiro Kawate ,  Andrew C. Lottes ,  James G. Vana, Jr. ,  Barbara L. Birrell ,  Alexander W. Barr

IPC: H05K1/00 ,  B32B7/12

CPC classification number: H05K3/361 ,  H01L2224/81 ,  H05K1/117 ,  H05K1/148 ,  H05K3/244 ,  H05K3/323 ,  H05K2201/09745 ,  Y10T156/10 ,  Y10T428/24917 ,  Y10T428/2804 ,  Y10T428/287

Abstract: Provided is a method of connecting conductive traces on one substrate to conductive traces on another substrate using an adhesive containing conductive particles and the resulting article.

Abstract translation: 提供了使用包含导电颗粒和所得制品的粘合剂将一个衬底上的导电迹线连接到另一衬底上的导电迹线的方法。

公开(公告)号：US07829985B2

公开(公告)日：2010-11-09

申请号：US12315721

申请日：2008-12-04

Applicant: Hyo Soo Lee ,  Sung Eun Park

Inventor： Hyo Soo Lee ,  Sung Eun Park

IPC: H01L23/495

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4864 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K3/06 ,  H05K3/242 ,  H05K3/243 ,  H05K3/282 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/09745 ,  H05K2203/0353 ,  H05K2203/0369 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.

Abstract translation: 具有半蚀刻接合焊盘和切割电镀线的球栅阵列（BGA）封装及其制造方法。 在BGA封装中，使用半蚀刻将电镀线切割成预定的不均匀焊接焊盘，从而增加焊盘和焊球之间的接触面积。 BGA封装包括具有第一电路图案和引线焊盘图案的第一外部层，其中芯片使用引线接合连接到引线接合焊盘。 第二外部层包括第二电路图案，切割电镀线图案和半蚀刻的不均匀焊球图案。 在第二外部层中，另一芯片安装在焊球垫上。 绝缘层，其具有介于所述第一外部层和所述第二外部层之间的通孔，并且使所述第一外部层与所述第二外部层电连接。

公开(公告)号：US20100279521A1

公开(公告)日：2010-11-04

申请号：US12061774

申请日：2008-04-03

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触 。

公开(公告)号：US20100263849A1

公开(公告)日：2010-10-21

申请号：US12067355

申请日：2006-09-19

Applicant: Masayuki Nakano ,  Yoshikazu Oshika

Inventor： Masayuki Nakano ,  Yoshikazu Oshika

IPC: F28F7/00 ,  B23P15/26 ,  C22C5/02

CPC classification number: C22C5/02 ,  B23K35/262 ,  B23K35/264 ,  B23K35/282 ,  B23K35/286 ,  B23K35/3006 ,  B23K35/3013 ,  B23K35/302 ,  B23K35/3033 ,  H01L21/50 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/04026 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15724 ,  H01L2924/19107 ,  H01L2924/351 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/3457 ,  H05K2201/09745 ,  Y02P70/611 ,  Y10T29/49393 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A heat sink (10) is disclosed which comprises a substrate (1), an electrode layer (2) formed on the substrate (1) and a solder layer (3) formed on the substrate (1) wherein the solder layer (3) provides a bonding strength of not less than 30 MPa and a shear strain of not less than 0.07. The heat sink may be a sub-mount which comprises a sub-mount substrate (1), an electrode layer (2) formed on the substrate (1) and a solder layer (3) formed on the substrate (1) wherein the electrode layer (2) is formed with a window portion (2A) having the solder layer (3) embedded therein and is connected to an outer peripheral area of the solder layer (3). A sub-mount that has a high strength of bonding between the solder layer (3) and a semiconductor device is provided at a reduced cost.

Abstract translation: 公开了一种散热器（10），其包括基板（1），形成在基板（1）上的电极层（2）和形成在基板（1）上的焊料层（3），其中焊料层（3） 提供不小于30MPa的接合强度和不小于0.07的剪切应变。 散热器可以是子安装件，其包括副安装基板（1），形成在基板（1）上的电极层（2）和形成在基板（1）上的焊料层（3），其中电极 层（2）形成有其中嵌入有焊料层（3）的窗口部分（2A），并且连接到焊料层（3）的外周区域。 以降低的成本提供了在焊料层（3）和半导体器件之间具有高粘合强度的子安装件。

公开(公告)号：US20100252312A1

公开(公告)日：2010-10-07

申请号：US12671153

申请日：2008-07-04

Applicant: Daniel Wolde-Giorgis ,  Thomas Kalich

Inventor： Daniel Wolde-Giorgis ,  Thomas Kalich

IPC: H05K1/16 ,  B32B3/00 ,  B23K1/20

CPC classification number: B23K35/025 ,  H01L23/13 ,  H01L23/3735 ,  H01L23/3737 ,  H01L24/29 ,  H01L24/31 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/75315 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2924/15747 ,  H05K1/0306 ,  H05K3/321 ,  H05K2201/09745 ,  H05K2201/10166 ,  H05K2203/1131 ,  Y10T428/24612 ,  H01L2924/00 ,  H01L2924/3512

Abstract: An assembly having a substrate and at least one component fastened thereon by sintering using a sintering agent, in particular sintering paste. The sintering agent is situated in a recess of the substrate that accommodates at least some areas of the component. A method for producing an assembly having a substrate and at least one component fastened thereon by sintering using a sintering agent, in particular sintering paste. The sintering agent is brought into a recess of the substrate that accommodates at least some areas of the component.

Abstract translation: 一种具有基底和至少一个部件的组件，所述组件通过使用烧结剂，特别是烧结膏进行烧结而紧固在其上。 烧结剂位于衬底的凹部中，其容纳组件的至少一些区域。 一种用于制造具有基底和至少一个部件的组件的方法，所述组件通过使用烧结剂，特别是烧结膏进行烧结而紧固在其上。 烧结剂被引入容纳至少部分区域的衬底的凹部中。

公开(公告)号：US20100236822A1

公开(公告)日：2010-09-23

申请号：US12498860

申请日：2009-07-07

Applicant: Toshiki FURUTANI ,  Takeshi FURUSAWA

Inventor： Toshiki FURUTANI ,  Takeshi FURUSAWA

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K1/187 ,  H05K3/205 ,  H05K3/243 ,  H05K3/244 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0949 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2224/0401

Abstract: A wiring board is formed with a substrate, conductive patterns laminated in the thickness direction of the substrate, multiple pads having a predetermined pitch and formed on the same layer as the conductive patterns, a conductive bonding layer arranged on each of the multiple pads, and an electronic component having electrodes. Here, the electronic component is arranged inside the substrate. The electrodes of the electronic component and the multiple pads are electrically connected to each other by means of bonding layers. Also, the height of each of the multiple pads is greater than the height of the conductive pattern adjacent to each pad. Moreover, a protective material related to the bonding layers is not formed at least on the layer where the pads and the first conductive patterns are formed.

Abstract translation: 布线板形成有基板，在基板的厚度方向上层叠的导电图案，具有预定间距的多个焊盘，并形成在与导电图案相同的层上，布置在多个焊盘的每一个上的导电接合层，以及 具有电极的电子部件。 这里，电子部件配置在基板的内部。 电子部件的电极和多个焊盘通过接合层彼此电连接。 此外，多个焊盘中的每一个的高度大于与每个焊盘相邻的导电图案的高度。 此外，至少在形成焊盘和第一导电图案的层上形成与结合层相关的保护材料。

公开(公告)号：US20100212947A1

公开(公告)日：2010-08-26

申请号：US12712034

申请日：2010-02-24

Applicant: Kimihiro YAMANAKA ,  Manabu ICHINOSE ,  Satoshi NAKAMURA

Inventor： Kimihiro YAMANAKA ,  Manabu ICHINOSE ,  Satoshi NAKAMURA

IPC: H05K1/18 ,  H05K1/00

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09627 ,  H05K2201/09745 ,  H05K2201/09854 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T428/24917 ,  H01L2224/05599

Abstract: According to one embodiment of the invention, a circuit board comprises a conductive layer including a land portion and a line portion connected to the land portion, and; a conductor connected to a surface of the land portion. A planar shape of the connected portion between the conductor and the land portion has a elongated shape along a width direction of the line portion. A part of the connected portion is located within an imaginary region formed by imaginarily extending the line portion toward the land portion.

Abstract translation: 根据本发明的一个实施例，电路板包括导电层，该导电层包括接地部分和连接到焊盘部分的线路部分， 连接到陆部的表面的导体。 导体与陆部之间的连接部分的平面形状沿着线部分的宽度方向具有细长形状。 连接部分的一部分位于通过将线部分向着陆部分的想象地延伸形成的虚拟区域内。

公开(公告)号：US20100190297A1

公开(公告)日：2010-07-29

申请号：US12714494

申请日：2010-02-28

Applicant: Charles W.C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W.C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L21/50 ,  H01L21/60

CPC classification number: H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L33/483 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/16152 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/09745 ,  H05K2201/10106 ,  H01L2224/05599

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post to form a cavity in the post, then mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 制造半导体芯片组件的方法包括提供柱和基座，将粘合剂安装在基座上，包括将柱插入粘合剂中的开口中，将基底安装在粘合剂上，包括使柱与基底中的孔对准， 然后将粘合剂在位于柱和基底之间的孔中的间隙中向上流动，固化粘合剂，然后蚀刻柱以在柱中形成空腔，然后将半导体器件安装在柱上，其中散热器 包括柱和基部，并且半导体器件延伸到空腔中，将半导体器件电连接到衬底并将半导体器件热连接到散热器。