公开(公告)号：US20030233133A1

公开(公告)日：2003-12-18

申请号：US10174349

申请日：2002-06-17

Inventor： Robert J. Greenberg ,  Alfred E. Mann ,  Neil Talbot ,  Jerry Ok

IPC: A61N001/375

CPC classification number: A61N1/375 ,  A61N1/0543 ,  A61N1/36046 ,  A61N1/3758 ,  H05K1/0306 ,  H05K3/321 ,  H05K3/328 ,  H05K3/361 ,  H05K3/4015 ,  H05K3/423 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2201/10295 ,  H05K2201/10977 ,  H05K2203/0733 ,  H05K2203/1446 ,  Y10T29/49155

Abstract: The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package, that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by one of several methods, including attachment by an electrically conductive adhesive, such as epoxy or polyimide, containing platinum metal flake in biocompatible glue; diffusion bonding of platinum bumps covered by an insulating layer; thermal welding of wire staples; or an integrated interconnect fabrication. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.

Abstract translation: 本发明涉及一种将气密密封的电子封装结合到电极或柔性电路的方法以及所得到的电子封装，其适于植入生物组织，例如用于视网膜或皮质电极阵列，以使视力恢复 对某些无意识的个人。 密封的电子封装通过几种方法之一直接接合到柔性电路或电极，包括通过导电粘合剂（例如环氧树脂或聚酰亚胺）附着，其包含生物相容性胶中的铂金属薄片; 由绝缘层覆盖的铂凸块的扩散接合; 线钉热焊接; 或集成互连制造。 所得到的电子装置是生物相容的并且适合长期植入生物体组织。

公开(公告)号：US06529105B1

公开(公告)日：2003-03-04

申请号：US09494358

申请日：2000-01-31

Applicant: Gerard Cachier ,  Jean-Yves Daden ,  Alain Grancher

Inventor： Gerard Cachier ,  Jean-Yves Daden ,  Alain Grancher

IPC: H01P308

CPC classification number: H01P1/047 ,  H05K1/0219 ,  H05K1/142 ,  H05K2201/1028

Abstract: A device, and a method for making the same, for bonding two millimeter elements, which include a substrate having an upper face and a lower face, a conducting line on the upper face and oriented substantially perpendicular to an edge of the substrate, and two continuous bounding zones on the upper face and along the edge of the substrate, each continuous bounding zone being electrically grounded, and having a length along said edge between about two and about five times the width of the conducting lines.

Abstract translation: 一种装置及其制造方法，用于将包括具有上表面和下表面的基板的两个毫米元件连接在上表面上的导线并基本上垂直于基板的边缘取向，并且两个元件 连续的边界区域在基板的上表面和边缘上，每个连续的边界区域是电接地的，沿着所述边缘的长度在导线宽度的大约两倍到五倍之间。

公开(公告)号：US20020134579A1

公开(公告)日：2002-09-26

申请号：US10104801

申请日：2002-03-22

Applicant: Mitsumi Electric Co. Ltd.

Inventor： Kenji Saito

IPC: H05K001/03

CPC classification number: H05K1/0259 ,  H05K3/361 ,  H05K9/0067 ,  H05K2201/1028 ,  H05K2203/175

Abstract: An electroconductive sheet is stuck on electrodes of an electronic device so as to electrically connect the electrodes with each other. Next, the electrodes are inserted into a corresponding connector. Finally, the electroconductive sheet is peeled from the electrodes.

Abstract translation: 将导电片粘贴在电子设备的电极上，以将电极彼此电连接。 接下来，将电极插入到相应的连接器中。 最后，导电片从电极剥离。

公开(公告)号：US20020074644A1

公开(公告)日：2002-06-20

申请号：US09741206

申请日：2000-12-19

Inventor： Robert L. Sankman

IPC: H01L023/053 ,  H01L023/12

CPC classification number: H05K3/4038 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4602 ,  H05K2201/1028 ,  H05K2203/0235 ,  H01L2224/05599

Abstract: A microelectronic substrate having a plurality of alternating substantially planar layers of dielectric material and conductive material, and further having a first surface and a second surface, wherein the dielectric material and the conductive material layers extend substantially perpendicularly between the first and second surfaces.

Abstract translation: 一种微电子衬底，其具有多个交替的基本平坦的电介质材料和导电材料层，并且还具有第一表面和第二表面，其中所述电介质材料和所述导电材料层在所述第一表面和所述第二表面之间基本垂直地延伸。

公开(公告)号：US06358094B1

公开(公告)日：2002-03-19

申请号：US09538698

申请日：2000-03-30

Applicant: Yakov Belopolsky ,  Jenn Tsao

Inventor： Yakov Belopolsky ,  Jenn Tsao

IPC: H01R2400

CPC classification number: H05K1/148 ,  H01R12/7082 ,  H01R12/7088 ,  H01R13/658 ,  H05K2201/0792 ,  H05K2201/097 ,  H05K2201/10272 ,  H05K2201/1028 ,  H05K2203/1572

Abstract: A low inductance power connector for reducing inductance in an electrical conductor is provided. An interface connector connects circuit boards together while reducing inductance and increasing current carrying capacity. The connector for connecting circuit boards comprises a first contact having a body, a first mating portion and a second mating portion, and a second contact having a body, a third mating portion and a fourth mating portion. The first and second mating portions are substantially parallel and disposed on opposite sides of the body of the first contact, and the third and fourth mating portions are substantially parallel and disposed on opposite sides of the body of the second contact.

Abstract translation: 提供了用于降低电导体中的电感的低电感电源连接器。 接口连接器将电路板连接在一起，同时减少电感和增加载流能力。 用于连接电路板的连接器包括具有主体，第一配合部分和第二配合部分的第一触点和具有主体，第三配合部分和第四配合部分的第二触点。 第一和第二配合部分基本上平行并且设置在第一接触件的主体的相对侧上，并且第三和第四配合部分基本上平行并且设置在第二接触件的主体的相对侧上。

公开(公告)号：US06316104B1

公开(公告)日：2001-11-13

申请号：US09446455

申请日：1999-12-29

Applicant: Masayuki Kumakura

Inventor： Masayuki Kumakura

IPC: D02G300

CPC classification number: H05K3/386 ,  C09J167/00 ,  H05K1/0393 ,  H05K2201/012 ,  H05K2201/0145 ,  H05K2201/0769 ,  H05K2201/1028 ,  H05K2203/122 ,  H05K2203/1545 ,  Y10T428/2933 ,  Y10T428/2938 ,  Y10T428/2958

Abstract: Adhesives and adhesive films based on polymer resins and containing a cationic scavenger are provided for circuit materials and flat cables with metallic wiring. The cationic scavenger reduces free cations in the adhesive and prevents the loss over time of insulation and adhesive strength provided to the circuit materials.

Abstract translation: 提供了基于聚合物树脂并含有阳离子清除剂的粘合剂和粘合剂膜，用于电路材料和具有金属布线的扁平电缆。 阳离子清除剂减少粘合剂中的游离阳离子，并防止绝缘时间的损失和提供给电路材料的粘合强度。

公开(公告)号：US06225573B1

公开(公告)日：2001-05-01

申请号：US09180978

申请日：1998-11-18

Applicant: Satoshi Nakamura

Inventor： Satoshi Nakamura

IPC: H01R1204

CPC classification number: H05K3/3405 ,  H01R12/52 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/305 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/083 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/09909 ,  H05K2201/1028 ,  H05K2201/1034 ,  H05K2203/0545 ,  H05K2203/104 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: There are provided a coating step for coating solder paste (3) onto the circuit board (1), a superimposing step for superimposing a connecting end (4a) of a terminal (4) also having a non-connecting end (4b) on the regions coated with solder paste (3), and a heating step for heating and melting the solder paste (3) in order to solder the connecting end (4a) onto the circuit board (1). A further step for coating adhesive material (6) onto the circuit board (1) is provided, and in the aforementioned superimposing step, the connecting end (4a) is brought into contact with the regions coated with the adhesive material (6). In the aforementioned heating step, the solder paste (3) is heated and caused to melt whilst the connecting end (4a) is in a bonded state with respect to the circuit board (1) by means of the adhesive material (6).

Abstract translation: 提供了一种用于将焊膏（3）涂覆到电路板（1）上的涂覆步骤，用于将也具有非连接端（4b）的端子（4）的连接端（4a）重叠在其上的叠加步骤 涂覆有焊膏（3）的区域，以及用于加热和熔化焊膏（3）的加热步骤，以将连接端（4a）焊接到电路板（1）上。 提供了将粘合剂材料（6）涂覆到电路板（1）上的另一步骤，并且在上述重叠步骤中，连接端（4a）与涂覆有粘合剂材料（6）的区域接触。 在上述加热步骤中，焊膏（3）被加热并熔化，同时连接端（4a）通过粘合材料（6）相对于电路板（1）处于接合状态。

公开(公告)号：US6062903A

公开(公告)日：2000-05-16

申请号：US92994

申请日：1998-06-08

Applicant: Kevin Joseph Hawes ,  Sean Michael Kelly ,  David Jay Vess

Inventor： Kevin Joseph Hawes ,  Sean Michael Kelly ,  David Jay Vess

IPC: H01R31/08 ,  H05K3/22

CPC classification number: H01R12/57 ,  H01R31/085 ,  H05K1/0265 ,  H05K3/222 ,  H05K2201/1028

Abstract: An improved interconnect apparatus for high power circuits that is low in cost and amenable for integration with low power circuits in a single electronic package. The interconnect apparatus includes serially connected surface mount bus bars bridging two or more metal pads or traces formed on a standard circuit board of the type used to package low power circuitry. The surface mount bus bars operate not only to conduct the higher currents, but also to draw heat out of the metal pads or intervening portions of the metal traces. This keeps the temperature within the capabilities of low power circuit board technology, and allows very narrow high power interconnects for reduced package size. Manufacturing cost advantages are achieved because the surface mount bus bars are assembled by automated pick-and-place equipment of the same type used for other surface mount components used in the package. In certain circumstances, a series of surface mount bus bars may be placed atop a continuous metal trace, or overlapped to provide a minimum resistance connection.

Abstract translation: 一种用于高功率电路的改进的互连装置，其成本低廉并且适于与单个电子封装中的低功率电路集成。 互连装置包括串联连接的表面安装汇流条，桥接形成在用于封装低功率电路的类型的标准电路板上的两个或更多个金属焊盘或迹线。 表面安装母线不仅用于传导较高的电流，而且还用于将热量从金属焊盘或金属迹线的中间部分吸出。 这将使温度保持在低功耗电路板技术的能力范围内，并允许非常窄的大功率互连以减少封装尺寸。 制造成本优势得到实现，因为表面贴装母线由用于包装中使用的其他表面贴装部件的相同类型的自动拾取和放置设备组装。 在某些情况下，一系列表面贴装母线可以放置在连续的金属迹线上，或重叠以提供最小电阻连接。

公开(公告)号：US5793611A

公开(公告)日：1998-08-11

申请号：US752009

申请日：1996-11-19

Applicant: Norio Nakazato ,  Shigeki Hirasawa ,  Shoji Masukawa ,  Heikichi Kuwahara

Inventor： Norio Nakazato ,  Shigeki Hirasawa ,  Shoji Masukawa ,  Heikichi Kuwahara

IPC: H05K7/20 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0201 ,  H05K1/0207 ,  H05K7/20509 ,  H05K1/0272 ,  H05K1/181 ,  H05K2201/0187 ,  H05K2201/0397 ,  H05K2201/062 ,  H05K2201/09063 ,  H05K2201/1028 ,  H05K2201/10416 ,  H05K2203/304

Abstract: An electronic device comprises a substrate having electronic parts, electric conductive wires for electrically connecting between the electronic parts, a front surface on which the electronic parts and electric conductive wires are mounted, a reverse surface and at least one electronic part back portion opposite to the electronic parts; and at least one high thermal conductivity member, a thermal conductivity coefficient thereof being higher than that of the substrate, the high thermal conductivity member being connected to the electronic part back portion while the high thermal conductivity member is opposite to the electronic parts in a substrate width direction to decrease a difference in temperature between the electronic parts.

Abstract translation: 电子设备包括具有电子部件的基板，用于电连接电子部件的导电线，安装有电子部件和导电线的前表面，反面以及与该电子部件相对的至少一个电子部件后部 电子零件; 和至少一个高导热性部件，其导热系数高于基板的导热系数，高导热性部件连接到电子部件背部，同时高导热性部件与基板中的电子部件相对 宽度方向以减小电子部件之间的温度差。

公开(公告)号：US5201974A

公开(公告)日：1993-04-13

申请号：US475578

申请日：1990-02-06

Applicant: Frederick A. West

Inventor： Frederick A. West

IPC: H05K1/00 ,  H05K1/09 ,  H05K3/20 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K3/4632 ,  H05K3/20 ,  H05K3/4617 ,  H05K7/06 ,  H05K1/0393 ,  H05K1/095 ,  H05K2201/0129 ,  H05K2201/09809 ,  H05K2201/09881 ,  H05K2201/1028 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1545 ,  H05K3/1275 ,  H05K3/366 ,  H05K3/4069 ,  H05K3/4614 ,  Y10S428/901 ,  Y10T156/1015 ,  Y10T29/49126

Abstract: Patterned electrically conductive structures, such as circuit elements, in single or multiple laminar form, and their manufacture. The basic laminar structure is made by sizing a removable substrate to substantially equal depth with an electrically conductive material over a given area configured as a circuit element and with an electrically non-conductive material elsewhere, bonding the respective sizing materials in place and together, and separating the substrate to leave a lamina of electrically conductive and non-conductive materials side-by-side. Face-to-face juxtaposition of such substrate-less laminae provides built-up or laminated products.

Abstract translation: 图案化的导电结构，例如单层或多层流形式的电路元件及其制造。 基本的层状结构是通过将可移除的衬底在给定的区域上形成与导电材料基本相同的深度来制造的，该给定区域被构造为电路元件，并且在其它地方使用不导电材料，将相应的施胶材料粘合在一起，并将它们结合在一起;以及 分离衬底以并排留下导电和非导电材料层。 这种无底板的面对面并置提供积层或层压产品。