公开(公告)号：US20170125349A1

公开(公告)日：2017-05-04

申请号：US15350393

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/683 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US09640887B2

公开(公告)日：2017-05-02

申请号：US15135413

申请日：2016-04-21

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram S. Viswanath

IPC: H02G3/04 ,  H01R12/79 ,  H01R12/62 ,  H05K1/14 ,  H05K3/36 ,  H01L23/498 ,  H01B7/04 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01R12/79 ,  H01B7/04 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R12/62 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H01L2224/0401

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

公开(公告)号：US09640508B2

公开(公告)日：2017-05-02

申请号：US14885356

申请日：2015-10-16

Applicant: FUJITSU LIMITED

Inventor： Taiki Uemura ,  Kozo Shimizu ,  Seiki Sakuyama

IPC: H01L23/00 ,  B23K35/26 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/81 ,  B23K35/26 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/13023 ,  H01L2224/13109 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16507 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75702 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81098 ,  H01L2224/81192 ,  H01L2224/81211 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/8191 ,  H01L2224/81948 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/0133 ,  H01L2924/20104 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10674 ,  H05K2203/047 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: An electrical apparatus includes a first electrical component; a second electrical component; and an In—Sn—Ag alloy connecting the first electrical component and the second electrical component, the In—Sn—Ag alloy containing AgIn2 and Ag2In, a Ag2In content being lower than a AgIn2 content.

公开(公告)号：US09633977B1

公开(公告)日：2017-04-25

申请号：US15040902

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Shiqun Gu ,  Urmi Ray ,  Ratibor Radojcic

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/10 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/92144 ,  H01L2924/19105 ,  H05K1/14 ,  H05K1/148 ,  H05K1/185 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10674 ,  H05K2203/0191

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

公开(公告)号：US20170077049A1

公开(公告)日：2017-03-16

申请号：US15120370

申请日：2014-03-26

Applicant: Mitsubishi Electric Corporation

Inventor： Takeshi YUASA ,  Kiyoshi ISHIDA ,  Yoshihiro TSUKAHARA ,  Kohei NISHIGUCHI

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/66 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/6683 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16227 ,  H05K1/0243 ,  H05K2201/10674 ,  H01L2924/00012

Abstract: A surface mount high-frequency circuit is configured such that a plurality of ground pads 41 and a plurality of external connection ground conductors 51 are discretely disposed to surround a signal line pad 42 and an external connection signal line conductor 52, and a plurality of interlayer connection ground conductors 31 and that a plurality of columnar ground conductors 12 are discretely disposed to surround an interlayer connection signal line conductor 32. Thus, it is possible to suppress radiation of an unnecessary signal to the outside using a simple production process that is completed by only a wafer process without separately preparing a component such as a shield cover case.

Abstract translation: 表面安装高频电路被配置为使得多个接地焊盘41和多个外部连接接地导体51离散地设置成围绕信号线焊盘42和外部连接信号线导体52以及多个中间层 连接接地导体31和多个柱状接地导体12离散地设置成围绕层间连接信号线导体32.因此，可以使用简单的生产过程来抑制对外部的不必要信号的辐射，该简单的生产过程由 仅仅是晶片工艺，而不需要单独地制备诸如屏蔽罩壳的部件。

公开(公告)号：US09591767B2

公开(公告)日：2017-03-07

申请号：US14290173

申请日：2014-05-29

Applicant: FUJIKURA LTD.

Inventor： Kazuhisa Itoi ,  Masahiro Okamoto

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/10 ,  H01L23/538 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/10 ,  H01L21/4857 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/08237 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11416 ,  H01L2224/11418 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13316 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/1336 ,  H01L2224/1339 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/73201 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80903 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8185 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8349 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15153 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/186 ,  H05K3/0061 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/0969 ,  H05K2201/10674 ,  Y10T29/49126 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/069 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2224/32 ,  H01L2924/00

Abstract: A component built-in board comprises stacked therein a plurality of printed wiring bases having a wiring pattern and a via formed on/in a resin base thereof, and comprises an electronic component built in thereto, wherein at least a portion of the plurality of printed wiring bases include a thermal wiring in the wiring pattern and include a thermal via in the via, at least one of the plurality of printed wiring bases has formed therein an opening where the electronic component is built, and has formed therein a heat-conducting layer and closely attached to a surface on an opposite side to an electrode formation surface of the electronic component built in to the opening, and the electronic component is fixed in the opening by an adhesive layer stacked on the heat-conducting layer, via a hole formed in a region facing onto the opening of the heat-conducting layer.

Abstract translation: 一种组件内置板，其中堆叠有多个印刷布线基底，其具有形成在其树脂基底上的布线图案和通孔，并且包括内置于其中的电子部件，其中多个印刷的至少一部分 布线基底包括布线图案中的热布线，并且在通孔中包括热通孔，多个印刷布线基底中的至少一个在其中形成有电子部件构建的开口，并且在其中形成有导热层 并且紧贴在与内置于开口部的电子部件的电极形成面相反一侧的面上，电子部件通过形成有孔的层叠在导热层上的粘接层固定在开口部 在面向导热层的开口的区域中。

公开(公告)号：US20170047240A1

公开(公告)日：2017-02-16

申请号：US15334569

申请日：2016-10-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L21/683 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20170025343A1

公开(公告)日：2017-01-26

申请号：US15284514

申请日：2016-10-03

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US20170018521A1

公开(公告)日：2017-01-19

申请号：US15215350

申请日：2016-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16157 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.

Abstract translation: 实施例装置包括电介质层，电介质层中的导电迹线和凸块焊盘。 导电迹线包括具有暴露的顶表面的第一部分，其中暴露的顶表面从电介质层的顶表面凹陷。 此外，凸块焊盘设置在导电迹线的第二部分上并与其电连接。

公开(公告)号：US09536556B2

公开(公告)日：2017-01-03

申请号：US14987083

申请日：2016-01-04

Applicant: Seagate Technology LLC

Inventor： Jon Paul Hurley ,  Bernard W. Bell ,  Steven Harlow Anderson Axdal

IPC: G11B5/10 ,  G11B7/127 ,  B23K1/00 ,  G11B13/04 ,  H01L23/488 ,  H01S5/02 ,  H01L23/00 ,  G11B5/105 ,  B23K35/26 ,  B23K35/30 ,  C22C5/02 ,  C22C13/00 ,  B23K35/24 ,  H01L21/60 ,  G11B5/012 ,  G11B5/60 ,  G11B5/00

CPC classification number: G11B7/127 ,  B23K1/0008 ,  B23K35/24 ,  B23K35/262 ,  B23K35/3013 ,  C22C5/02 ,  C22C13/00 ,  G11B5/012 ,  G11B5/105 ,  G11B5/6005 ,  G11B5/6088 ,  G11B13/04 ,  G11B2005/0021 ,  H01L23/488 ,  H01L24/15 ,  H01L2021/60022 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01S5/0216 ,  H05K2201/10674

Abstract: A heat assisted magnetic recording (HAMR) assembly includes a slider, a laser diode and solder connections between the laser diode and the slider. The solder connections mechanically and electrically attach the laser diode to the slider. Each solder connection has a total volume per unit area (i.e., height) of less than or equal to about 15 μm. The solder connections have a first intermetallic zone adjacent to the laser diode, a second intermetallic zone adjacent to the slider, and a eutectic zone of eutectic material between the first and second intermetallic zones. The eutectic zone occupies greater than or equal to about 35% of the total volume per unit area of the solder connection.

Abstract translation: 热辅助磁记录（HAMR）组件包括滑块，激光二极管和激光二极管与滑块之间的焊接连接。 焊接连接将激光二极管机械和电连接到滑块。 每个焊接连接具有小于或等于约15μm的每单位面积的总体积（即高度）。 焊接连接具有与激光二极管相邻的第一金属间区域，与滑块相邻的第二金属间区域和在第一和第二金属间区域之间的共晶材料的共晶区域。 共晶区域占据焊料连接单位面积总体积的大约或等于约35％。