公开(公告)号：US20240074127A1

公开(公告)日：2024-02-29

申请号：US18221461

申请日：2023-07-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chen-Yu Wang ,  Pai-Sheng Cheng ,  Huan-Kuen Chen

IPC: H05K9/00 ,  H05K1/05 ,  H05K1/18

CPC classification number: H05K9/0037 ,  H05K1/05 ,  H05K1/181 ,  H05K9/0088 ,  H05K2201/0104 ,  H05K2201/10977

Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.

公开(公告)号：US20240074041A1

公开(公告)日：2024-02-29

申请号：US18234642

申请日：2023-08-16

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Gwo-Shyan Sheu ,  Kuo-Liang Huang ,  Hsin-Hao Huang ,  Pei-Wen Wang ,  Yu-Chen Ma

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0268 ,  H05K1/111

Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.

公开(公告)号：US20230163061A1

公开(公告)日：2023-05-25

申请号：US17975692

申请日：2022-10-28

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yu-Chen Ma ,  Pei-Wen Wang ,  Hsin-Hao Huang ,  Gwo-Shyan Sheu

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/26175

Abstract: In a semiconductor package, flow guiding strips are provided on a guiding area of a flexible substrate to separate a chip and the flexible substrate such that a filling material flowing between the chip and the flexible substrate can squeeze out the air between the chip and the flexible substrate to improve the reliability of the semiconductor package.

公开(公告)号：US11651974B2

公开(公告)日：2023-05-16

申请号：US17161818

申请日：2021-01-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu ,  Fei-Jain Wu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/562

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

公开(公告)号：US20230135424A1

公开(公告)日：2023-05-04

申请号：US17896171

申请日：2022-08-26

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Wen-Cheng Hsu ,  Chen-Yu Wang ,  Chih-Ming Kuo ,  Chwan-Tyaw Chen ,  Lung-Hua Ho

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/311 ,  H01L21/3213 ,  C23C18/54 ,  C23C28/02 ,  C25D7/12

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

公开(公告)号：US20230102718A1

公开(公告)日：2023-03-30

申请号：US17860224

申请日：2022-07-08

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Hsueh-Shun Yeh

IPC: G03F7/42 ,  G03F7/11

Abstract: A method of stripping photoresist includes the steps of pattering a photoresist located on a substrate to generate an opening showing the substrate, forming a film including a first portion located on a top surface of the photoresist and a second portion located on a surface of the substrate, attaching a tape on the first portion, removing the tape and the first portion to show the top surface of the photoresist, and contacting the top surface and a lateral surface of the photoresist with a photoresist stripping solution to strip the photoresist. The photoresist can be removed completely by increasing its contacting area with the photoresist stripping solution.

公开(公告)号：US11606860B2

公开(公告)日：2023-03-14

申请号：US17504635

申请日：2021-10-19

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Gwo-Shyan Sheu ,  Hsin-Hao Huang ,  Yu-Chen Ma ,  Chia-Hsin Yen

IPC: H05K1/02 ,  H05K1/18

Abstract: A flexible circuit board includes a flexible substrate, a chip and a patterned circuit layer. A surface of the flexible substrate is separated into a working area and a nonworking area according to a cutting line. The chip is disposed on the working area. The patterned circuit layer is disposed on the surface and includes signal transmission wires and bypass wires, the bypass wires are not electrically connected to the chip. Each of the bypass wires includes a bypass transmission portion located on the working area and an anti-peeling portion located on the nonworking area. A blank area exists between the anti-peeling area and the bypass transmission portion, and the cutting line passes through the blank area. A distance between 100 um and 400 um exists from the anti-peeling portion to the cutting line.

公开(公告)号：US20230044473A1

公开(公告)日：2023-02-09

申请号：US17837145

申请日：2022-06-10

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yin-Chen Lin ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

IPC: H05K1/02 ,  H05K1/11

Abstract: A double-sided flexible circuit board includes a flexible substrate, a first circuit layer, a second circuit layer, an insulating protection layer and a plurality of through circuit lines. The first and second circuit layers are located on a top surface and a bottom surface of the flexible substrate, respectively. The insulating protection layer covers a supporting line of the second circuit layer such that the supporting line is located between the flexible substrate and the insulating protection layer. The insulating protection layer can provide electrical insulation to the supporting line of the second circuit layer to avoid short circuit conditions of the double-sided flexible circuit board during test.

公开(公告)号：US20220328334A1

公开(公告)日：2022-10-13

申请号：US17690121

申请日：2022-03-09

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Hsu-Chi Lee ,  Pi-Yu Peng ,  Chun-Te Lee

IPC: H01L21/673

Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.

公开(公告)号：US11322437B2

公开(公告)日：2022-05-03

申请号：US17038237

申请日：2020-09-30

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yu-Chen Ma ,  Hsin-Hao Huang ,  Wen-Fu Chou ,  Gwo-Shyan Sheu

IPC: H01L23/498 ,  H01L23/00

Abstract: A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.