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公开(公告)号：USD861009S1
公开(公告)日：2019-09-24
申请号：US29583908
申请日：2016-11-09
Applicant: PHISON ELECTRONICS CORP. , Gettop opto technology co., ltd
Designer： Yuan-Sheng Lien , Hung-Chin Lee , Tsung-Ping Yu , Hsiao-Wen Fan , Ming-Hsien Lee , Tzu-Jen Wang
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公开(公告)号：US10424391B2
公开(公告)日：2019-09-24
申请号：US15811695
申请日：2017-11-14
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Szu-Wei Chen , Yu-Siang Yang
IPC: G11C29/00 , G11C29/52 , G11C16/10 , G06F12/02 , G06F11/10 , G11C16/30 , G11C16/08 , G11C16/26 , G11C11/56 , G11C16/04
Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.
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公开(公告)号：US10416902B2
公开(公告)日：2019-09-17
申请号：US15091583
申请日：2016-04-06
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hsueh-Yuan Wu
Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: determining whether a relative relation between a first wear value of first physical erasing units initially configured to be programmed based on a first programming mode and a second wear value of second physical erasing units initially configured to be programmed based on a second programming mode is satisfied; and when the relative relation between the first wear value and the second wear value is not satisfied, selecting one or more third physical erasing units from second physical erasing units. The method also includes: programming the one or more third physical erasing units based on the first programming mode to store first data received from a host system into the one or more third physical erasing units.
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公开(公告)号：US20190278480A1
公开(公告)日：2019-09-12
申请号：US15956749
申请日：2018-04-19
Applicant: PHISON ELECTRONICS CORP.
Inventor： Siu-Tung Lam , Ming-Yen Lee , Kuo-Lung Lee
Abstract: A block management method, a memory control circuit unit and a memory storage apparatus for managing a plurality of physical blocks are provided. The method includes reading user data from a first physical block among physical blocks to obtain a plurality of parameters; inputting the parameters corresponding to the first physical block into a machine learning based block recognizer to group the first physical block into a first block group or a second block group according to an output result of the machine learning based block recognizer; establishing a first and second block mapping tables; mapping logical addresses of the first and second block mapping tables to the physical blocks belonging to the first and second block groups. The parameters may comprise at least one of a read busy time parameter, an error bit position parameter and a storage retention parameter. A machine learning operation may be performed using first and second test physical blocks, and corresponding parameters, as training data. A usage status may be determined according to the parameters, and blocks with a usage status of good may be used first to evenly use all the physical blocks.
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公开(公告)号：US10403365B2
公开(公告)日：2019-09-03
申请号：US15452742
申请日：2017-03-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Shin Chang , Wei-Yung Chen
Abstract: An exemplary embodiment of the disclosure provides a switch module which includes a first conductive unit, a first switch unit and a first electrostatic protection module. The first electrostatic protection module is coupled between the first conductive unit and the first switch unit. The first electrostatic protection module includes a first protection circuit and a first inductor circuit. The first inductor circuit includes a first inductor unit, and the first inductor circuit is coupled between the first protection circuit and the first conductive unit. Accordingly, the transmission efficiency of the switch (or multiplexer) for high speed signal can be improved.
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Patent Agency Ranking
公开(公告)号：US10338854B2
公开(公告)日：2019-07-02
申请号：US14846830
申请日：2015-09-07
Applicant: PHISON ELECTRONICS CORP.
Inventor： Kok-Yong Tan , Horng-Sheng Yan
Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.
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公开(公告)号：US20190189228A1
公开(公告)日：2019-06-20
申请号：US15890326
申请日：2018-02-06
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Hsiang Lin , Yu-Cheng Hsu
Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.
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公开(公告)号：US10310739B2
公开(公告)日：2019-06-04
申请号：US15690286
申请日：2017-08-30
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chien-Wen Chen , Che-Yueh Kuo
Abstract: A memory management method is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a valid data parameter based on a valid data amount of valid data stored in a plurality of physical erasing units, and obtaining a first threshold value based on the valid data parameter. The method also includes: obtaining a first determination parameter based on a number of a plurality of first physical erasing units, and the first physical erasing units are physical erasing units being programmed for storing data by using a single-page programming mode. The method further includes: performing a garbage collection operation if the first determination parameter is greater than the first threshold value.
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公开(公告)号：US10297297B2
公开(公告)日：2019-05-21
申请号：US14578471
申请日：2014-12-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen
Abstract: A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.
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公开(公告)号：US10235094B2
公开(公告)日：2019-03-19
申请号：US15060622
申请日：2016-03-04
Applicant: PHISON ELECTRONICS CORP.
Inventor： Bo-Cheng Ko
Abstract: A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes recording a flush command counting (FCC) value, and updating the FCC value whenever receiving a flush command from a host system. The method further includes getting a first physical erasing unit as an active physical unit and determining whether the FCC value is greater than a FCC value threshold. The method further includes setting a writing mode of the active physical unit as a first writing mode if the FCC value is greater than the FCC value threshold, and setting the writing mode of the active physical unit as a second writing mode if the FCC value is not greater than the FCC value threshold.
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