公开(公告)号：US11031274B2

公开(公告)日：2021-06-08

申请号：US16578062

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin Shih ,  Chih-Cheng Lee

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium.

公开(公告)号：US11018120B2

公开(公告)日：2021-05-25

申请号：US16434075

申请日：2019-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US20210013585A1

公开(公告)日：2021-01-14

申请号：US16506654

申请日：2019-07-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee ,  Chun Chen Chen ,  Yuanhao Yu

IPC: H01Q1/22 ,  H01L23/66

Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.

公开(公告)号：US10734704B2

公开(公告)日：2020-08-04

申请号：US16197352

申请日：2018-11-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01Q1/22 ,  H01Q23/00 ,  H01Q9/04 ,  H01Q21/06 ,  H01L23/66 ,  H01Q21/00 ,  H01L23/00

Abstract: An antenna package includes a patterned antenna structure and an encapsulant. The patterned antenna structure includes a first surface, a second surface opposite the first surface and a third surface extended between the first surface and the second surface. The encapsulant is disposed on the first surface of the patterned antenna structure. The third surface of the patterned antenna structure includes a first portion covered by the encapsulant and a second portion exposed from the encapsulant.

公开(公告)号：US10515884B2

公开(公告)日：2019-12-24

申请号：US14624388

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

公开(公告)号：US10354969B2

公开(公告)日：2019-07-16

申请号：US15665289

申请日：2017-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin Shih ,  Chih-Cheng Lee

IPC: H01L21/48 ,  H01L23/00

Abstract: A substrate structure includes a dielectric layer, a first circuit layer, at least one conductive structure and a first protective layer. The first circuit layer is disposed adjacent to a first surface of the dielectric layer. The conductive structure includes a first portion and a second portion. The first portion is disposed on the first circuit layer. The first protective layer is disposed on the dielectric layer and contacts at least a portion of a sidewall of the first portion of the conductive structure. The first circuit layer and the conductive structure are integrally formed.

公开(公告)号：US10083902B2

公开(公告)日：2018-09-25

申请号：US15208569

申请日：2016-07-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang Su ,  Chih-Cheng Lee ,  Cheng-Lin Ho

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

公开(公告)号：US09754906B2

公开(公告)日：2017-09-05

申请号：US14750880

申请日：2015-06-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/11464 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/13099

Abstract: The present disclosure relates to a package substrate. The package substrate includes a patterned conductive layer and conductive pillars. Each of the conductive pillars includes a first portion and a second portion, where the first portion contacts the patterned conductive layer at one end of the first portion, and the second portion is adjacent to another end of the first portion. A thickness of the first portion is greater than a thickness of the second portion. Side surfaces of the first portion are substantially coplanar to side surfaces of the second portion.

公开(公告)号：US09721799B2

公开(公告)日：2017-08-01

申请号：US14536253

申请日：2014-11-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin Shih ,  Chih-Cheng Lee

IPC: H01L21/288 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L21/288 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/838 ,  H01L2224/92144

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes.

公开(公告)号：US09583427B2

公开(公告)日：2017-02-28

申请号：US15138107

申请日：2016-04-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng Lee ,  Yuan Chang Su ,  Cheng-Lin Ho ,  Chung-Ming Wu ,  You-Lung Yen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract translation: 本公开涉及半导体衬底，半导体封装结构及其制造方法。 一种方法包括提供衬底和载体层。 衬底包括第一图案化金属层，与第一图案化金属层间隔开的第二图案化金属层，以及设置在第一图案化金属层和第二图案化金属层之间的介电层。 电介质层覆盖第二图案化金属层。 电介质层限定暴露第二图案化金属层的第一开口，并且还限定从第一图案化金属层延伸到第二图案化金属层的通孔。 导电材料设置在通孔中并将第一图案化金属层电连接到第二图案化金属层。 载体层限定暴露第二图案化金属层的第二开口。