公开(公告)号：US20050196885A1

公开(公告)日：2005-09-08

申请号：US10793317

申请日：2004-03-03

Applicant: Jeffrey Pollard ,  Michael Miller

Inventor： Jeffrey Pollard ,  Michael Miller

IPC: B41J2/16 ,  B81C1/00 ,  H01L21/00

CPC classification number: B81C1/00087 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1634 ,  B81B2201/052

Abstract: The described embodiments relate to slotted substrates and methods of forming same. One exemplary method forms a first slot portion into a first surface of a substrate, the first slot portion defining a footprint at the first surface. The method also forms a second slot portion through the first slot portion; and, forms a third slot portion through a second surface of the substrate sufficiently to intercept the second slot portion to form a fluid-handling slot through the substrate.

Abstract translation: 所描述的实施例涉及开槽衬底及其形成方法。 一种示例性方法形成到衬底的第一表面中的第一槽部分，第一槽部分在第一表面处限定占地面积。 该方法还通过第一槽部分形成第二槽部分; 并且通过所述基板的第二表面形成足以拦截所述第二槽部分以形成通过所述基板的流体处理槽的第三槽部分。

公开(公告)号：US20030160023A1

公开(公告)日：2003-08-28

申请号：US10373235

申请日：2003-02-24

Applicant: BENO CORPORATION

Inventor： In-Yao Lee ,  Chih-Ching Chen

IPC: C03C025/68

CPC classification number: B81C1/0042 ,  B01L3/0241 ,  B41J2/16 ,  B41J2/1629 ,  B41J2/1631 ,  B81B2201/052 ,  B81B2203/0392 ,  B81C1/00595 ,  B81C2201/0136

Abstract: A method of manufacturing a fluid injection device. The method of the present invention applies a compensated geometric shape of the unetched isolating portions to increase the additional compensated portion for etching, or the ion implanting process to reduce the etching rate of the unetched isolating portions. Thus, crosstalk or overshoot in the isolating portions of the fluid injection device can be reduced, and the fluid injection device can be precisely manufactured in a small size.

Abstract translation: 一种制造流体注射装置的方法。 本发明的方法应用未蚀刻绝缘部分的补偿几何形状以增加用于蚀刻的附加补偿部分，或离子注入工艺以降低未蚀刻绝缘部分的蚀刻速率。 因此，可以减少流体注入装置的隔离部分中的串扰或过冲，并且能够精确地制造流体注射装置。

公开(公告)号：US20020042985A1

公开(公告)日：2002-04-18

申请号：US09942548

申请日：2001-08-31

Inventor： Kia Silverbrook

IPC: B41J002/04 ,  H05B003/00

CPC classification number: B41J2/1645 ,  B41J2/14427 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1648 ,  B81B3/007 ,  B81B2201/031 ,  B81B2201/036 ,  B81B2201/052 ,  Y10T29/42 ,  Y10T29/49083 ,  Y10T29/49401

Abstract: A thermal bend actuator (6) is provided with upper arms (23, 25, 26) and lower arms (27, 28) which are non planar, so increasing the stiffness of the arms. The arms (23, 25, 26, 27, 28) may be spaced transversely of each other and do not overly each other in plan view, so enabling all arms to be formed by depositing a single layer of arm forming material.

Abstract translation: 热弯曲致动器（6）设置有不平坦的上臂（23,25,26）和下臂（27,28），因此增加了臂的刚度。 臂（23,25,26,27,28）可以彼此横向地间隔开，并且在平面图中不会彼此过大，从而能够通过沉积单层臂形成材料来形成所有臂。

公开(公告)号：US5804083A

公开(公告)日：1998-09-08

申请号：US653050

申请日：1996-05-28

Applicant: Yorishige Ishii ,  Tetsuya Inui ,  Hirotsugu Matoba ,  Susumu Hirata ,  Masaharu Kimura ,  Hajime Horinaka ,  Shingo Abe ,  Hiroshi Onda

Inventor： Yorishige Ishii ,  Tetsuya Inui ,  Hirotsugu Matoba ,  Susumu Hirata ,  Masaharu Kimura ,  Hajime Horinaka ,  Shingo Abe ,  Hiroshi Onda

IPC: B29C67/00 ,  B29D99/00 ,  B41J2/16 ,  B81B3/00 ,  B81C1/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  B41J2/05 ,  C23F1/00

CPC classification number: B81C1/00595 ,  B41J2/16 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2002/14346 ,  B81B2201/052 ,  B81C2201/0109

Abstract: Method of forming a complex, minute three-dimensional structure, known as micromachining, which includes forming a plurality of thin films at least one of which is provided as a temporary layer composed of a lower layer made of an organic material and an upper layer made of an amphoteric metal material which is formed on the lower layer; and selectively removing the temporary layer to provide a three-dimensional structure. The temporary layer may comprise a composite sacrificial layer of photoresist and aluminum.

Abstract translation: 形成复杂的微小三维结构的方法，称为微加工，其包括形成多个薄膜，其中至少一个薄膜被设置为由有机材料制成的下层和上层制成的临时层 形成在下层上的两性金属材料; 并选择性地去除临时层以提供三维结构。 临时层可以包括光致抗蚀剂和铝的复合牺牲层。

公开(公告)号：US4863560A

公开(公告)日：1989-09-05

申请号：US234994

申请日：1988-08-22

Applicant: William G. Hawkins

Inventor： William G. Hawkins

IPC: B41J2/05 ,  B41J2/16 ,  B81B1/00 ,  C30B29/06 ,  G02B6/36 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: B81C1/00126 ,  B41J2/1601 ,  B41J2/1626 ,  B41J2/1631 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3085 ,  B81B2201/052 ,  B81B2203/0338 ,  G02B6/3644 ,  G02B6/3692

Abstract: Three dimensional silicon structures are fabricated from (100) silicon wafers by a single side, multiple step ODE etching process. All etching masks are formed one on top of the other prior to the initiation of etching, with the coarsest mask formed last and used first. Once the coarse anisotropic etching is completed, the coarse mask is removed and the finer anisotropic etching is done. The preferred embodiment is described using a thermal ink jet channel plate as the three dimensional structure, where coarse etching step provides the reservoir and the fine etching step provides the ink channels.

公开(公告)号：US20180265353A1

公开(公告)日：2018-09-20

申请号：US15761192

申请日：2015-11-05

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Chien-Hua Chen ,  Devin A. Mourey ,  Michael G. Groh

IPC: B81C99/00 ,  B81C1/00 ,  B41J2/155 ,  B41J2/16

CPC classification number: B81C99/008 ,  B01L3/0268 ,  B41J2/155 ,  B41J2/1603 ,  B41J2/1637 ,  B41J2202/19 ,  B41J2202/20 ,  B41J2202/21 ,  B81B2201/052 ,  B81B2201/058 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C1/00309 ,  B81C2201/0188 ,  B81C2203/0154

Abstract: Examples include a device comprising integrated circuit dies molded into a molded panel. The molded panel has three-dimensional features formed therein, where the three-dimensional features are associated with the integrated circuit dies. To form the three-dimensional features, a feature formation material is deposited, the molded panel is formed, and the feature formation material is removed.

公开(公告)号：US20180147848A1

公开(公告)日：2018-05-31

申请号：US15817963

申请日：2017-11-20

Applicant: CANON KABUSHIKI KAISHA

Inventor： Atsushi Teranishi ,  Masaya Uyama

IPC: B41J2/16 ,  B81B1/00 ,  B81C1/00

CPC classification number: B41J2/16 ,  B41J2/14145 ,  B41J2/1603 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1642 ,  B41J2/1645 ,  B41J2/1646 ,  B41J2002/14467 ,  B81B1/004 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C2201/019 ,  B81C2203/032

Abstract: A method for forming a film that covers a side wall of a through hole in a substrate having the through hole, the method including, in the following order, the steps of providing a substrate having a through hole that passes therethrough from a first surface to a second surface, which is a surface opposite to the first surface, forming, on the first surface, a lid member that blocks an opening of the through hole open on the first surface, recessing, in a direction away from the first surface, a surface of the lid member that blocks the opening by removing part of the lid member through the opening, and forming a film that covers the side wall of the through hole.

公开(公告)号：US20170275153A1

公开(公告)日：2017-09-28

申请号：US15080356

申请日：2016-03-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Ming Chen ,  Ping-Yin Liu ,  Chung-Yi Yu ,  Yeur-Luen Tu

IPC: B81B7/00 ,  B81C1/00 ,  H01L23/00

CPC classification number: B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/052 ,  B81C1/00269 ,  B81C1/00357 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/036 ,  H01L24/03 ,  H01L24/09 ,  H01L2224/02163 ,  H01L2224/05082 ,  H01L2224/05109 ,  H01L2224/05117 ,  H01L2224/05124 ,  H01L2224/05138 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/1461

Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

公开(公告)号：US09695515B2

公开(公告)日：2017-07-04

申请号：US14913771

申请日：2013-08-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Roger A. McKay, Jr. ,  Patrick Sadik

IPC: C23F1/16 ,  B41J2/16 ,  B81C1/00

CPC classification number: C23F1/16 ,  B41J2/1609 ,  B41J2/1629 ,  B41J2/1631 ,  B81B2201/052 ,  B81C1/00119

Abstract: An example provides a method including providing a substrate including an area having a plurality of pores and etching the area of the substrate to remove the plurality of pores to form a recess in the substrate. In some examples, the recess may form, at least in part, a device.

公开(公告)号：US09624101B2

公开(公告)日：2017-04-18

申请号：US13878205

申请日：2010-10-21

Applicant: Peter Mardilovich ,  Anthony M. Fuller ,  Qingqiao Wei ,  Rio Rivas ,  David Kamp

Inventor： Peter Mardilovich ,  Anthony M. Fuller ,  Qingqiao Wei ,  Rio Rivas ,  David Kamp

IPC: B82B3/00 ,  C25D11/02 ,  C25D11/04 ,  C25D11/26 ,  B81C1/00

CPC classification number: B82B3/0014 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C1/00206 ,  C25D11/022 ,  C25D11/045 ,  C25D11/26

Abstract: An article is provided, the article including a substrate having a surface with a first wettability characteristic. A nano-structure array is formed on the surface of the substrate to provide a nano-structured surface having a second wettability characteristic. A thin-layer surface coating is formed on the nano-structured surface, the thin-layer surface coating being configured to tune the nano-structured surface to a target wettability characteristic.