中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

1023 records (took 0.024 seconds)

    METHOD FOR FABRICATING PRINTED CIRCUIT BOARD
    51.
    发明申请
    METHOD FOR FABRICATING PRINTED CIRCUIT BOARD 有权
    印刷电路板制作方法

    公开(公告)号：US20100011573A1

    公开(公告)日：2010-01-21

    申请号：US12504339

    申请日：2009-07-16

    Applicant: Ki-Hyun KIM ,  Se-Ho Park ,  Seok-Myong Kang ,  Young-Min Lee

    Inventor： Ki-Hyun KIM ,  Se-Ho Park ,  Seok-Myong Kang ,  Young-Min Lee

    IPC: H05K3/10

    CPC classification number: H05K3/4069 ,  H05K1/0393 ,  H05K1/095 ,  H05K3/12 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09981 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A method for fabricating a printed circuit board is provided. The method includes manufacturing a base film including a first side and a second side opposite to the first side; printing a first wiring on the first side with a high-viscosity conductive material having a viscosity of 5,000 to 300,000 centipoise (CPS); forming a via-hole that passes through both sides of the base film, and passes by the first wiring; and printing a second wiring on the second side with a low-viscosity conductive material having a viscosity of 100 to 5,000 CPS. The low-viscosity conductive material is applied to an inner wall of the via-hole to conductively connect the first wiring to the second wiring.

    Abstract translation: 提供一种制造印刷电路板的方法。 该方法包括制造包括第一侧和与第一侧相对的第二侧的基膜; 用粘度为5000至300,000厘泊（CPS）的高粘度导电材料在第一侧印刷第一布线; 形成穿过基膜的两侧的通孔，并通过第一布线; 以及使用粘度为100-5,000CPS的低粘度导电材料在第二侧上印刷第二布线。 将低粘度导电材料施加到通孔的内壁，以将第一布线导电连接到第二布线。

    Wiring, display device and method of manufacturing the same
    54.
    发明授权
    Wiring, display device and method of manufacturing the same 有权
    接线，显示装置及其制造方法

    公开(公告)号：US07626125B2

    公开(公告)日：2009-12-01

    申请号：US10800861

    申请日：2004-03-16

    Applicant: Hiroki Nakamura

    Inventor： Hiroki Nakamura

    IPC: H05K1/09

    CPC classification number: H01L21/76843 ,  H01L21/76852 ,  H01L21/76874 ,  H01L21/76885 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L2221/1078 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0347 ,  H05K2203/072 ,  Y10T29/49117

    Abstract: The present invention provides a wiring, a display device, and a method of manufacturing the same. A first metal diffusion-preventing layer is formed on a substrate or on a circuit element formed on the substrate. Then, a metal wiring layer is selectively formed on the first metal diffusion-preventing layer by an electroless metal plating method or a metal electroplating method. Further, the undesired portion of the first metal diffusion-preventing layer is removed. Finally, a second metal diffusion-preventing layer is formed selectively by an electroless metal plating method in a manner to cover the metal wiring layer or both a seed layer and the metal wiring layer.

    Abstract translation: 本发明提供一种布线，显示装置及其制造方法。 在基板或形成在基板上的电路元件上形成第一金属防扩散层。 然后，通过无电金属电镀法或金属电镀法，在第一金属防止扩散层上选择性地形成金属布线层。 此外，去除了第一金属防扩散层的不希望的部分。 最后，以覆盖金属布线层或晶种层和金属布线层的方式，通过化学镀金属法选择性地形成第二金属防扩散层。

    Multilayer wiring board, multilayer wiring board unit and electronic device
    55.
    发明申请
    Multilayer wiring board, multilayer wiring board unit and electronic device 审中-公开
    多层布线板，多层布线板单元和电子设备

    公开(公告)号：US20090236143A1

    公开(公告)日：2009-09-24

    申请号：US12292845

    申请日：2008-11-26

    Applicant: Naoki Nakamura

    Inventor： Naoki Nakamura

    IPC: H05K1/11 ,  H05K5/00

    CPC classification number: H05K1/115 ,  H05K1/113 ,  H05K3/4652 ,  H05K2201/0347 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0959 ,  H05K2201/096

    Abstract: A multilayer wiring board that includes multiple wiring layers, multiple insulating layers stacked alternately with the multiple wiring layers to form a multilayer structure, a first via, and a second via. The first via is in the shape of a recess and made of a conductor covering an inner surface of a hole penetrating through insulating layers and having a bottom on an inner wiring layer of the wiring layers that has insulating layers on both the upper and lower sides thereof. The second via is in the shape of a recess and made of a conductor covering an inner surface of a hole penetrating through insulating layers in the direction opposite to the direction of the hole for the first via and having a bottom on the inner wiring layer at a position corresponding to the bottom of the hole for the first via.

    Abstract translation: 一种多层布线板，包括多个布线层，多个绝缘层与多个布线层交替堆叠以形成多层结构，第一通孔和第二通孔。 第一通孔为凹槽形状，由覆盖穿透绝缘层的孔的内表面的导体制成，并且在上下两侧具有绝缘层的布线层的内部布线层上具有底部 其中。 第二通孔为凹槽的形状，由导体覆盖的导体覆盖孔的内表面，孔的内表面沿着与第一通孔的孔的方向相反的方向穿过绝缘层，并且在内部布线层上具有底部 对应于用于第一通孔的孔的底部的位置。

    MULTILAYER BUILD-UP WIRING BOARD
    56.
    发明申请
    MULTILAYER BUILD-UP WIRING BOARD 有权
    多层建筑接线板

    公开(公告)号：US20090173523A1

    公开(公告)日：2009-07-09

    申请号：US12406009

    申请日：2009-03-17

    Applicant: Naohiro HIROSE ,  Honjin En

    Inventor： Naohiro HIROSE ,  Honjin En

    IPC: H05K1/02

    CPC classification number: H01L29/40 ,  H01L21/4763 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/03 ,  H05K3/064 ,  H05K3/244 ,  H05K3/382 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09681 ,  H05K2203/1178

    Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 μm. The reason is as follows. If the diameter of the mesh hole is less than 75 μm, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 μm, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 μm. The reason is as follows. If the distance is less than 100 μm, the solid layer cannot function. If the distance exceeds 2000 μm, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

    Abstract translation: 上固体层35和上固体层59的网孔35a和59a形成为彼此重叠，使得层间树脂绝缘层50的绝缘性能不降低。 这里，每个网孔的直径优选为75〜300μm。 原因如下。 如果网孔的直径小于75μm，则难以将上，下网孔叠置在一起。 如果直径超过300μm，则层间树脂绝缘层的绝缘性能变差。 此外，网眼之间的距离优选为100〜2000μm。 原因如下。 如果距离小于100um，则固体层不能起作用。 如果距离超过2000μm，则发生层间树脂绝缘膜的绝缘性劣化。

    HOLE IN PAD THERMAL MANAGEMENT
    58.
    发明申请
    HOLE IN PAD THERMAL MANAGEMENT 有权
    密封垫热管理

    公开(公告)号：US20090090540A1

    公开(公告)日：2009-04-09

    申请号：US11868871

    申请日：2007-10-08

    Applicant: Lee H. Tullidge ,  Leonard De Oto ,  Tim Larson ,  Patrick O'Keefe ,  Herb Gertz

    Inventor： Lee H. Tullidge ,  Leonard De Oto ,  Tim Larson ,  Patrick O'Keefe ,  Herb Gertz

    IPC: H01B13/00 ,  H05K1/00

    CPC classification number: H05K1/0206 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/1492 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A device and method of heat sinking a surface mount device (SMD) component. In an example method through holes are formed in a printed circuit board (PCB), a first copper layer is electroless plated in the holes, a second copper layer is standard plated in the holes and surrounding surfaces of the PCB, a third copper layer is masked and pulse plated in the holes, the holes are filled with non-conductive material and then is sanded flush with the second copper layer. A fourth copper layer electroless plated on the PCB over the area of the holes, a fifth copper layer (or pad) plated on the PCB over the area of the holes, and a surface mount device is attached to the fifth copper layer.

    Abstract translation: 散热表面贴装器件（SMD）元件的器件和方法。 在一个示例性方法中，通孔形成在印刷电路板（PCB）中，第一铜层被无电镀在孔中，第二铜层标准镀在PCB的孔和周围表面中，第三铜层是 屏蔽并脉冲电镀在孔中，孔中填充有非导电材料，然后与第二铜层进行砂光冲洗。 在PCB上的无孔电镀第四铜层，在孔的区域上镀有PCB上的第五铜层（或焊盘），以及表面贴装装置附着在第五铜层上。

Patent Agency Ranking