公开(公告)号：US20150282323A1

公开(公告)日：2015-10-01

申请号：US14663921

申请日：2015-03-20

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Wataru Kaneda ,  Akio Rokugawa

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0222 ,  H05K1/0225 ,  H05K1/0298 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/116 ,  H05K3/26 ,  H05K3/381 ,  H05K3/4673 ,  H05K3/4676 ,  H05K2201/0191 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/0347 ,  H05K2201/068 ,  H05K2201/09227 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2203/0514

Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.

Abstract translation: 布线基板包括形成在芯层的一个表面上的第一布线层，形成在芯层的一个表面上以覆盖第一布线层的第一绝缘层，嵌入第一绝缘层中的通孔布线， 第二布线层，形成在第一绝缘层的第一表面上，以及比形成在第一绝缘层的第一表面上的第一绝缘层更薄的第二绝缘层，以覆盖第二布线层。 第一布线层包括焊盘和设置在焊盘周围的平面层。 通孔布线的一个端面从第一绝缘层的第一表面露出并直接接合到第二布线层。 通孔布线的另一个端面直接接合到第一绝缘层中的焊盘。

公开(公告)号：US20140345924A1

公开(公告)日：2014-11-27

申请号：US13902149

申请日：2013-05-24

Applicant: Nokia Corporation

Inventor： Mark Lee ALLEN ,  Chris BOWER ,  Darryl COTTON

IPC: H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0272 ,  H01L23/52 ,  H01L24/00 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24997 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/2919 ,  H01L2224/82101 ,  H01L2224/82138 ,  H01L2224/8284 ,  H01L2224/82862 ,  H01L2224/82874 ,  H01L2224/82877 ,  H01L2224/82986 ,  H01L2224/8385 ,  H01L2224/92144 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H05K1/092 ,  H05K1/097 ,  H05K3/101 ,  H05K3/107 ,  H05K2201/0257 ,  H05K2201/0302 ,  H05K2201/09036 ,  H05K2201/09227 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49117 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A substrate including a fluid reservoir and a connected fluid channel, the fluid reservoir positioned away from a component region of the substrate, the fluid channel configured to extend from the fluid reservoir to guide an electrically conductive fluid from the fluid reservoir at a reservoir end of the fluid channel through the fluid channel to a component end of the fluid channel, the component end extending to the component region of the substrate to enable the formation of an electrical connection to a connector of an electronic component appropriately positioned in the component region, formation of the electrical connection allowing the electronic component to be interconnected to other electronic components using one or more of the fluid reservoir and fluid channel.

Abstract translation: 包括流体储存器和连接的流体通道的基板，所述流体储存器远离所述基板的部件区域定位，所述流体通道被配置为从所述流体储存器延伸以在所述流体储存器的储存器端部处从所述流体储存器引导导电流体 通过流体通道的流体通道流到流体通道的部件端，部件端部延伸到基板的部件区域，以使得能够形成与适当地定位在部件区域中的电子部件的连接器的电连接，形成 的电连接，允许使用一个或多个流体储存器和流体通道将电子部件互连到其他电子部件。

公开(公告)号：US08864518B2

公开(公告)日：2014-10-21

申请号：US13745835

申请日：2013-01-20

Applicant: International Business Machines Corporation

Inventor： Jian Ming

IPC: H01R13/66

CPC classification number: H01R12/712 ,  G02B6/42 ,  H01R13/46 ,  H01R13/6466 ,  H01R13/648 ,  H01R2201/04 ,  H05K1/0213 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/09227 ,  H05K2201/10189

Abstract: A stacked connector component includes a housing, connectors at a front opening of the housing and arranged in a stacked formation within one or more columns, and a for and exposed at the connectors. The pins include high-speed pins routed within the housing to a bottom side thereof and low-speed pins routed within the housing to a back side or a top side thereof. A circuit board includes pin pads connectable to the pins and disposed on a substrate. The pin pads include high-speed signal pin pads for the high-speed signal pins. The substrate includes contiguous high-speed areas in which the high-speed signal pin pads for the high-speed pins are located, between which no pin pads are located.

Abstract translation: 堆叠的连接器部件包括壳体，位于壳体的前开口处的连接器，并且布置在一个或多个柱内的堆叠结构中，以及用于和暴露在连接器处。 这些销包括在壳体内布置到其底侧的高速销和在壳体内布置到其背侧或顶侧的低速销。 电路板包括可连接到引脚并设置在基板上的引脚焊盘。 引脚焊盘包括用于高速信号引脚的高速信号引脚焊盘。 衬底包括连接的高速区域，在高速区域中高速引脚的高速信号引脚焊盘位于其间，在其间没有引脚焊盘。

公开(公告)号：US08803003B2

公开(公告)日：2014-08-12

申请号：US13525531

申请日：2012-06-18

Applicant: Paul L. Mantiply ,  Straty Argyrakis

Inventor： Paul L. Mantiply ,  Straty Argyrakis

IPC: H05K1/11

CPC classification number: H05K1/0228 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/11 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/10704 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A circuit board is provided which includes a plurality of signal pairs of connectors. The signal pairs of connectors are disposed in a triangular grouping of three signal pairs of connectors such that a first connector of each signal pair is located at a vertex of the triangular grouping. A second connector of each signal pair is located at a side of the triangular grouping adjacent to the vertex of the first connector. The signal pairs may be differential pairs.

Abstract translation: 提供了包括多个信号对连接器的电路板。 连接器的信号对被布置成三个三组信号对的连接器，使得每个信号对的第一连接器位于三角形分组的顶点。 每个信号对的第二连接器位于与第一连接器的顶点相邻的三角形组的一侧。 信号对可以是差分对。

公开(公告)号：US20140209371A1

公开(公告)日：2014-07-31

申请号：US14164338

申请日：2014-01-27

Applicant: Steven E. Minich ,  Mark R. Gray

Inventor： Steven E. Minich ,  Mark R. Gray

IPC: H05K1/11 ,  H05K3/10 ,  H05K3/42

CPC classification number: H05K1/141 ,  H01R12/724 ,  H01R12/735 ,  H01R13/6587 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/14 ,  H05K3/306 ,  H05K2201/044 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2201/10295 ,  Y10T29/49165

Abstract: In accordance with the various embodiments disclosed herein, electrical connector footprints, such as printed circuit boards, is described comprising one or more of signal traces that each include a first section that extends parallel to the linear array direction and a second section extends in a direction that is different than the linear array direction.

Abstract translation: 根据本文公开的各种实施例，描述了诸如印刷电路板的电连接器覆盖区，其包括一个或多个信号迹线，每个信号迹线包括平行于线性阵列方向延伸的第一部分，第二部分沿着方向 这与线性阵列方向不同。

公开(公告)号：US20140209358A1

公开(公告)日：2014-07-31

申请号：US13751450

申请日：2013-01-28

Applicant: JOHN ANDREW LEBENS ,  David Paul Trauernicht ,  Yongcai Wang ,  Ronald Steven Cok

Inventor： JOHN ANDREW LEBENS ,  David Paul Trauernicht ,  Yongcai Wang ,  Ronald Steven Cok

IPC: H05K1/02

CPC classification number: H05K1/0296 ,  G06F3/044 ,  H05K1/02 ,  H05K1/0289 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09681 ,  H05K2201/09727 ,  Y10T428/26

Abstract: An electrical conductor includes a substrate having micro-channels formed in the substrate. A plurality of spaced-apart first micro-wires is located on or in the micro-channels, the first micro-wires extending across the substrate in a first direction. A plurality of spaced-apart second micro-wires is located on or in the micro-channels, the second micro-wires extending across the substrate in a second direction different from the first direction. Each second micro-wire is electrically connected to at least two first micro-wires and at least one of the second micro-wires has a width less than the width of at least one of the first micro-wires.

Abstract translation: 电导体包括在衬底中形成有微通道的衬底。 多个间隔开的第一微电线位于微通道上或微通道中，第一微电线在第一方向上延伸穿过衬底。 多个间隔开的第二微电线位于微通道上或微通道中，第二微电线沿与第一方向不同的第二方向延伸穿过衬底。 每个第二微线电连接到至少两个第一微线，并且至少一个第二微线的宽度小于第一微线中的至少一个的宽度。

公开(公告)号：US20140206207A1

公开(公告)日：2014-07-24

申请号：US13745835

申请日：2013-01-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jian Ming

IPC: H01R13/46 ,  H05K1/02

CPC classification number: H01R12/712 ,  G02B6/42 ,  H01R13/46 ,  H01R13/6466 ,  H01R13/648 ,  H01R2201/04 ,  H05K1/0213 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/09227 ,  H05K2201/10189

Abstract: A stacked connector component includes a housing, connectors at a front opening of the housing and arranged in a stacked formation within one or more columns, and a for and exposed at the connectors. The pins include high-speed pins routed within the housing to a bottom side thereof and low-speed pins routed within the housing to a back side or a top side thereof. A circuit board includes pin pads connectable to the pins and disposed on a substrate. The pin pads include high-speed signal pin pads for the high-speed signal pins. The substrate includes contiguous high-speed areas in which the high-speed signal pin pads for the high-speed pins are located, between which no pin pads are located.

公开(公告)号：US20140158401A1

公开(公告)日：2014-06-12

申请号：US13805716

申请日：2012-12-14

Applicant: Ming-hung Shih ,  Zuomin Liao

Inventor： Ming-hung Shih ,  Zuomin Liao

IPC: H05K1/02

CPC classification number: H05K1/025 ,  H05K2201/09227 ,  H05K2201/09727

Abstract: The present invention provides a display panel and a wiring structure thereof. The wiring structure comprises a plurality of metal wires extending across a first wiring region, a second wiring region, and a third wiring region. The first wiring region adjoins the second wiring region. The second wiring region adjoins the third wiring region. A line width of an nth metal wire in the second wiring region is a, and a distance between the nth metal wire and an n+1th metal wire is b, where n≧1. When n is taken as different values, a/(a+b) is a constant value. According to the above method, the coverage ratio in the seal coating region by the metal wires is not changed to avoid the problem of uneven curing of the sealant. The performance stability of the display panel is thus not impacted.

Abstract translation: 本发明提供一种显示面板及其布线结构。 布线结构包括跨越第一布线区域延伸的多个金属布线，第二布线区域和第三布线区域。 第一布线区域邻接第二布线区域。 第二布线区域邻接第三布线区域。 第n布线区域的第n金属线的线宽为a，第n金属线与第n + 1金属线的距离为b，n≥1。 将n取为不同值时，a /（a + b）为常数值。 根据上述方法，金属丝的密封涂覆区域的覆盖率不变化，以避免密封剂固化不均匀的问题。 因此显示面板的性能稳定性不受影响。

公开(公告)号：US08746925B2

公开(公告)日：2014-06-10

申请号：US13600352

申请日：2012-08-31

Applicant: Hua-Chen Fan ,  Te-Hen Lo ,  Cheng-Wei Chang

Inventor： Hua-Chen Fan ,  Te-Hen Lo ,  Cheng-Wei Chang

IPC: F21V21/00

CPC classification number: H05K1/0296 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09772 ,  H05K2201/10106

Abstract: A circuit board circuit apparatus and a light source apparatus including a substrate, a circuit layer, and at least one electronic component are disclosed. The circuit layer is formed on a surface of the substrate. The circuit layer includes a first circuit and a second circuit which are coplanar-disposed. The at least one electronic component is disposed on the circuit layer and connected with the circuit layer. Each electronic component has a first contact and a second contact. At least a part of the second circuit is disposed between the at least one electronic component and the first circuit. The at least one electronic component crosses over the second circuit, so that the second circuit penetrates through the bottom of the electronic component between the first contact and the second contact.

Abstract translation: 公开了一种电路板电路装置和包括基板，电路层和至少一个电子部件的光源装置。 电路层形成在基板的表面上。 电路层包括共面布置的第一电路和第二电路。 至少一个电子部件设置在电路层上并与电路层连接。 每个电子部件具有第一接触和第二接触。 第二电路的至少一部分设置在至少一个电子部件和第一电路之间。 所述至少一个电子部件跨越所述第二电路，使得所述第二电路在所述第一触点和所述第二触点之间穿过所述电子部件的底部。

公开(公告)号：US20140153172A1

公开(公告)日：2014-06-05

申请号：US13705747

申请日：2012-12-05

Applicant: Gary Brist

Inventor： Gary Brist

IPC: H05K1/02 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/111 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The present disclosure provides techniques for creating a symmetrical ball grid array pattern for an integrated circuit package. The ball grid array includes a symmetrical pattern of circuit connection points, wherein the symmetrical pattern is derived from a base hexagonal pattern that is repeated in at least one or more sections of the ball grid array.

Abstract translation: 本公开提供了用于创建用于集成电路封装的对称球栅阵列图案的技术。 球栅阵列包括电路连接点的对称图案，其中对称图案从在球栅阵列的至少一个或多个部分中重复的基本六边形图案导出。