公开(公告)号：US20130001606A1

公开(公告)日：2013-01-03

申请号：US13566291

申请日：2012-08-03

Applicant: Yu-Sik KIM ,  Woo-Sung HAN

Inventor： Yu-Sik KIM ,  Woo-Sung HAN

IPC: H05K1/11 ,  H01L27/15

CPC classification number: H05K1/0295 ,  H01L25/0753 ,  H01L2224/16225 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/0949 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2203/173

Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount includes a base substrate having first and second surfaces, a conductive pattern on the first surface, first and second pairs of first and second electrodes on the second surface and vias extending through the base substrate between the first and second surfaces. The conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes.

Abstract translation: 提供一种适用于可安装在其上的设备的AC和DC操作的子座，包括这种子座的发光设备以及制造这种子座的方法。 子座包括具有第一表面和第二表面的基底基底，第一表面上的导电图案，第二表面上的第一和第二对第一和第二电极以及在第一和第二表面之间延伸穿过基底的通孔。 导电图案包括第一组安装部分和沿着第一对第一和第二电极之间的第一电路径的两个通孔部分，以及第二组安装部分和沿第二电路的第二组电路之间的两个通孔部分 第一和第二电极，通孔部分将导电图案的各个部分连接到相应的电极。

公开(公告)号：US08336203B2

公开(公告)日：2012-12-25

申请号：US12759011

申请日：2010-04-13

Applicant: Yu-Hsu Lin

Inventor： Yu-Hsu Lin

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K1/00 ,  G06F17/5068 ,  H05K1/0245 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09318

Abstract: A printed circuit board layout method includes the following steps. A printed circuit board with a signal layer, and a pair of differential transmission lines positioned on the signal layer is provided. A first distance is determined, when the distance between the pair of differential transmission lines is greater or less than the first distance, an eye width and an eye height of an eye diagram obtained at output terminals of the pair of differential transmission lines increases. A second distance less than the first distance is set between the pair of differential transmission lines which makes the eye width and the eye height meet requirement of the differential transmission lines for the eye diagram.

Abstract translation: 印刷电路板布局方法包括以下步骤。 提供了具有信号层的印刷电路板和位于信号层上的一对差动传输线。 确定第一距离，当一对差动传输线之间的距离大于或小于第一距离时，在一对差动传输线的输出端获得的眼图的眼睛宽度和眼睛高度增加。 在一对差分传输线之间设置小于第一距离的第二距离，使得眼睛的眼睛宽度和眼睛高度满足眼图的差动传输线的要求。

公开(公告)号：US08330054B2

公开(公告)日：2012-12-11

申请号：US12771500

申请日：2010-04-30

Applicant: Mitsuru Honjo ,  Daisuke Yamauchi ,  Kei Nakamura

Inventor： Mitsuru Honjo ,  Daisuke Yamauchi ,  Kei Nakamura

IPC: H05K1/16

CPC classification number: G11B5/4846 ,  G11B5/484 ,  H05K1/0245 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: A plurality of wiring traces are formed on a base insulating layer, and a metal layer is formed on the opposite surface of the base insulating layer. Two adjacent wiring traces constitute a transmission line pair. The width of the wiring trace is set to not more than 250 μm, and the distance between the adjacent wiring traces is set to not less than 8 μm. The thickness of the base insulating layer is selected to cause differential impedance of the transmission line pair to be not less than 10 Ω and not more than 50 Ω.

Abstract translation: 在基底绝缘层上形成多个布线迹线，并且在基底绝缘层的相对表面上形成金属层。 两个相邻的布线迹线构成传输线对。 布线迹线的宽度设定为不大于250μm，并且相邻布线迹线之间的距离设定为不小于8μm。 选择基极绝缘层的厚度使传输线对的差分阻抗不小于10Ω; 不超过50个

公开(公告)号：US20120032865A1

公开(公告)日：2012-02-09

申请号：US13254326

申请日：2010-04-23

Applicant: Hiroshi Toyao ,  Noriaki Ando

Inventor： Hiroshi Toyao ,  Noriaki Ando

IPC: H01Q1/38 ,  H01Q21/00 ,  H01Q19/10 ,  H01P3/08

CPC classification number: H01P1/2005 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01P3/08 ,  H01Q9/42 ,  H01Q15/008 ,  H01Q15/0086 ,  H01Q15/14 ,  H01Q21/065 ,  H05K1/0236 ,  H05K1/036 ,  H05K1/165 ,  H05K2201/0191 ,  H05K2201/09318

Abstract: A structural body of the invention includes a first conductor plane (1), a plurality of second conductor planes (4) of which at least a portion is provided facing the first conductor plane (1), and a transmission line (6), having an open end, which is disposed between the first conductor plane (1) and the second conductor plane (4), electrically connected to any one conductor plane of the first conductor plane (1) or the second conductor plane (4) through a conductor connection portion (5) and provided facing the other conductor plane. A unit structure including at least the second conductor plane (4), the transmission line (6), and the conductor connection portion (5) is repeatedly disposed.

Abstract translation: 本发明的结构体包括第一导体平面（1），多个第二导体平面（4），其至少部分设置成面对第一导体平面（1），以及传输线（6），其具有 布置在第一导体平面（1）和第二导体平面（4）之间的开口端通过导线与第一导体平面（1）或第二导体平面（4）的任何一个导体平面电连接 连接部分（5）并面向另一个导体平面设置。 重复设置至少包括第二导体平面（4），传输线（6）和导体连接部分（5）的单元结构。

公开(公告)号：US08084692B2

公开(公告)日：2011-12-27

申请号：US11924416

申请日：2007-10-25

Applicant: Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

Inventor： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

IPC: H05K1/03

CPC classification number: H05K1/024 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T156/1013

Abstract: An apparatus having reduced noise coupling includes a core layer having an upper and lower surface, the upper and lower surface each including a copper sheet layer, a pre-preg layer having an upper surface and a lower surface, the upper surface of the pre-preg layer coupled to the lower surface of the core layer, a core insulating layer having an upper surface and a lower surface, the upper surface of the core insulating layer coupled to the lower surface of the pre-preg layer, a return current reference layer disposed on the lower surface of the core insulator layer and high-speed signal traces disposed on the upper surface of the core insulating layer, each of the high speed signal traces disposed on a pedestal defined by a section of the pre-preg layer and the core insulating layer, each pedestal being separated by an air gap disposed between adjacent pedestals.

Abstract translation: 具有降低的噪声耦合的装置包括具有上表面和下表面的芯层，所述上表面和下表面各自包括铜片层，具有上表面和下表面的预浸层， 耦合到芯层的下表面的芯层绝缘层，具有上表面和下表面的芯绝缘层，芯绝缘层的上表面耦合到预浸层的下表面，返回电流参考层 设置在芯绝缘体层的下表面和设置在芯绝缘层的上表面上的高速信号迹线，每个高速信号迹线设置在由预浸层的一部分限定的基座上， 芯绝缘层，每个基座由设置在相邻基座之间的气隙分隔开。

公开(公告)号：US08071882B2

公开(公告)日：2011-12-06

申请号：US11911914

申请日：2006-04-19

Applicant: Yoshihiko Okajima ,  Katsunori Yashima ,  Keiji Takano ,  Takuya Okada

Inventor： Yoshihiko Okajima ,  Katsunori Yashima ,  Keiji Takano ,  Takuya Okada

IPC: H05K1/03

CPC classification number: H05K1/0203 ,  F21K9/00 ,  F21Y2115/10 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2924/13091 ,  H05K1/0233 ,  H05K1/028 ,  H05K1/056 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/0061 ,  H05K3/281 ,  H05K3/386 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/086 ,  H05K2201/09318 ,  H05K2201/0989 ,  H05K2201/10106 ,  H05K2203/0191 ,  H05K2203/063 ,  H05K2203/302 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To provide a thin metal base circuit board which can be not only installed on a flat portion but also closely attached to a side or bottom surface of a case or to a stepped or curved portion and which is excellent in heat dissipation performance, electrical insulating performance and flexibility; a process for its production; and a hybrid integrated circuit, an LED module and a bright, ultra-long-life LED light source employing it. A metal base circuit board having insulating layers and conductive circuits or metal foils alternately laminated, characterized in that the thickness of each conductive circuit or metal foil is from 5 μm to 450 μm, each insulating layer is made of a cured product of a resin composition comprising an inorganic filler and a thermosetting resin, and the thickness of each insulating layer is from 9 μm to 300 μm; and a hybrid circuit board employing it.

Abstract translation: 为了提供一种薄的金属基底电路板，其不仅可以安装在平坦部分上，而且可以紧密地附接到壳体的侧面或底面，或者台阶或弯曲部分，并且散热性能优异，电绝缘性能 灵活性; 一个生产过程; 和混合集成电路，LED模块和采用它的明亮，超长寿命的LED光源。 具有交替层叠绝缘层和导电电路或金属箔的金属基电路板，其特征在于，各导电电路或金属箔的厚度为5μm〜450μm，绝缘层由树脂组合物的固化物 包括无机填料和热固性树脂，并且每个绝缘层的厚度为9μm至300μm; 和采用它的混合电路板。

公开(公告)号：US07952676B2

公开(公告)日：2011-05-31

申请号：US12002173

申请日：2007-12-14

Applicant: Seung-Bae Lee ,  Jung-Man Lim ,  Se-ll Kim

Inventor： Seung-Bae Lee ,  Jung-Man Lim ,  Se-ll Kim

IPC: G02F1/1345 ,  H01R4/66 ,  H01R13/58 ,  H01R9/03

CPC classification number: G02F1/13452 ,  H01R12/7076 ,  H01R12/721 ,  H01R13/658 ,  H05K1/0218 ,  H05K1/0393 ,  H05K2201/0715 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/09318

Abstract: Provided is a connection structure capable of reducing the distortion of a signal. The connection structure includes a first interconnection layer including a plurality of signal lines configured to transmit an operating signal generated by a driver to a receiver; a second interconnection layer including at least one ground line configured to connect the driver and ground terminals of the receiver; and an insulating layer interposed between the first and second interconnection layers to electrically insulate the signal lines from the ground line.

Abstract translation: 提供能够减少信号失真的连接结构。 连接结构包括：第一互连层，包括被配置为将由驾驶员生成的操作信号传送到接收器的多个信号线; 第二互连层，包括被配置为连接接收器的驱动器和接地端子的至少一个接地线; 以及插入在第一和第二互连层之间以将信号线与接地线电绝缘的绝缘层。

公开(公告)号：US20110083881A1

公开(公告)日：2011-04-14

申请号：US12969478

申请日：2010-12-15

Applicant: Vinh T. Nguyen ,  Claude A.S. Hamrick

Inventor： Vinh T. Nguyen ,  Claude A.S. Hamrick

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces and including a first nonconductive substrate having a first conductive material affixed to a first side thereof to form a first ground plane, a plurality of elongated first conductive traces formed on a second side of the first non-conductive substrate and having transverse widths of 50 microns or less and rising above the upper surface of the first substrate to a height equal to or greater than the widths thereof such that a transverse cross section of the first conductive traces has a height-to-width ratio equal to or exceeding 1, adjacent ones of the first traces being separated from each other by first elongated spaces, the first conductive traces being variously useful as ground lines, signal lines and/or power lines.

Abstract translation: 一种具有电隔离紧密间隔的电流载流迹线并包括第一非导电基底的多层电路器件，所述第一非导电基底具有固定到其第一侧的第一导电材料以形成第一接地平面;多个细长的第一导电迹线，形成在第二侧 第一非导电衬底并且具有50微米或更小的横向宽度并且在第一衬底的上表面上方升高到等于或大于其宽度的高度，使得第一导电迹线的横截面具有高度 宽度比等于或超过1，相邻的第一迹线通过第一细长空间彼此分开，第一导电迹线在各种不同地用作接地线，信号线和/或电力线。

公开(公告)号：US20110030997A1

公开(公告)日：2011-02-10

申请号：US12549376

申请日：2009-08-28

Applicant: SHOU-KUO HSU

Inventor： SHOU-KUO HSU

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0253 ,  H05K1/16 ,  H05K2201/09318 ,  H05K2201/09727

Abstract: A flexible printed circuit board (FPCB) includes a differential pair arranged in a signal layer and a ground sheet arranged in a ground layer. The differential pair includes a number of section pairs, each of which includes two sections arranged in two transmission lines of the differential pair respectively. The ground sheet is opposite to a space between the two transmission lines of the differential pair. The differential pair is equivalent to a filter which includes several capacitors and several inductors. Each of the plurality of section pairs can achieve a desired characteristic impedance by adjusting a first distance between each section and the ground sheet, and a second distance between the two sections of each of the plurality of section pairs.

Abstract translation: 柔性印刷电路板（FPCB）包括布置在信号层中的差分对和布置在接地层中的接地片。 差分对包括多个部分对，每个部分对分别包括分别布置在差分对的两条传输线中的两个部分。 接地片与差分对的两条传输线之间的空间相对。 差分对相当于一个滤波器，它包括几个电容器和几个电感器。 多个部分对中的每一个可以通过调整每个部分和接地片之间的第一距离以及多个部分对中的每一个的两个部分之间的第二距离来实现期望的特性阻抗。

公开(公告)号：US07880286B2

公开(公告)日：2011-02-01

申请号：US12222986

申请日：2008-08-21

Applicant: Si-Hoon Lee ,  Eun-Seok Song

Inventor： Si-Hoon Lee ,  Eun-Seok Song

IPC: H01L23/52

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09318 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract translation: 胶片封装可以包括带布线基板，安装在带布线基板上的半导体芯片，以及设置在半导体芯片和带布线基板之间的模塑料。 带状布线基板可以包括具有上表面和下表面的膜。 通风口可能会穿透电影。 上层金属层可以设置在膜的上表面上并且包括输入端子图案和/或输出端子图案。 输入端子图案可以包括接地端子图案和/或电源端子图案。 下部金属层可以设置在膜的下表面上并且包括接地层和/或功率层。 接地层和功率层可以至少覆盖芯片安装区域。