公开(公告)号：US07786579B2

公开(公告)日：2010-08-31

申请号：US11752449

申请日：2007-05-23

Applicant: Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

Inventor： Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/116 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K2201/09454 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.

Abstract translation: 提供具有集成电路的微电子封装。 微电子封装包括多个电介质层压层，铜电路在介电层压层之间，其中铜电路包括电路迹线，以及球栅阵列/焊盘电极阵列，可操作地连接到铜电路，从而导通发生。 此外，靠近铜电路和球栅阵列/接地栅阵列的连接，保护铜舌低于电路迹线的延伸线，使得保护铜舌防止电路迹线受到在 电介质层压层或球栅阵列/焊盘阵列。

公开(公告)号：US07745933B2

公开(公告)日：2010-06-29

申请号：US11739515

申请日：2007-04-24

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

公开(公告)号：US20090188705A1

公开(公告)日：2009-07-30

申请号：US12020534

申请日：2008-01-26

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/09

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。

公开(公告)号：US20090159327A1

公开(公告)日：2009-06-25

申请号：US12389456

申请日：2009-02-20

Applicant: Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H05K1/11 ,  H05K1/00

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract translation: 一种印刷电路板，包括芯基板，形成在所述芯基板上并包括第一绝缘层的堆积层，形成在所述第一绝缘层上的导体层和形成在所述导体层上的第二绝缘层，以及一个或 在第一绝缘层上形成更多的布线图案。 导体层包括导体部分，并且导体部分分别具有跨越布线图案彼此面对的切口部分。

公开(公告)号：US07479857B2

公开(公告)日：2009-01-20

申请号：US11524112

申请日：2006-09-19

Applicant: William E. McKinzie, III

Inventor： William E. McKinzie, III

IPC: H01P7/00

CPC classification number: H01G4/35 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/16 ,  H01P1/2005 ,  H01P1/211 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/0239 ,  H05K1/115 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/09809 ,  H01L2924/00

Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Particular embodiments include clusters of small vias that effectively function as one large via, thereby increasing stop band bandwidth and maximizing parallel plate capacitance. Cluster vias can be configured to additionally provide a shielded and impedance matched route within the interior area of the cluster through which signal vias can connect transmission lines disposed in planes lying above and below the PPW. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.

Abstract translation: 教导系统和方法阻止平行板波导（PPW）结构中电磁波的传播。 谐振通孔的周期阵列用于在PPW中产生宽带高频阻带，同时允许DC和低频波传播。 具体实施例包括有效地用作一个大通孔的小通孔簇，从而增加阻带带宽并最大化平行板电容。 集群通孔可以被配置为在簇的内部区域内另外提供屏蔽和阻抗匹配的路由，信号通孔可以通过该通孔连接布置在PPW上方和下方的平面中的传输线。 重要的应用包括诸如电路板，陶瓷模块和半导体芯片的分层电子设备中的电磁降噪。

公开(公告)号：US20080290510A1

公开(公告)日：2008-11-27

申请号：US11752449

申请日：2007-05-23

Applicant: Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

Inventor： Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

IPC: H01L23/485

CPC classification number: H05K1/116 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K2201/09454 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.

Abstract translation: 提供具有集成电路的微电子封装。 微电子封装包括多个电介质层压层，铜电路在介电层压层之间，其中铜电路包括电路迹线，以及球栅阵列/焊盘电极阵列，可操作地连接到铜电路，从而导通发生。 此外，靠近铜电路和球栅阵列/接地栅阵列的连接，保护铜舌低于电路迹线的延伸线，使得保护铜舌防止电路迹线受到在 电介质层压层或球栅阵列/焊盘阵列。

公开(公告)号：US07441221B2

公开(公告)日：2008-10-21

申请号：US11251770

申请日：2005-10-18

Applicant: Taketsugu Kawamichi ,  Hiroshi Nakamura ,  Eiichi Konno

Inventor： Taketsugu Kawamichi ,  Hiroshi Nakamura ,  Eiichi Konno

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H05K1/116 ,  H05K3/0005 ,  H05K2201/09454 ,  H05K2201/09536

Abstract: An apparatus generates design information on a via hole that passes through predetermined layers of a multilayer wiring board, by storing information on at least one of a shape and a size of a land to be provided around the via hole. When designing a via hole that passes through a plurality of internal layers of the wiring board, the land information for an internal layer is applied to each internal layer through which the via hole passes.

Abstract translation: 一种装置通过存储要通过孔的形状和尺寸的至少一个形状的信息，在穿过多层布线板的预定层的通孔上产生设计信息。 当设计通过布线板的多个内层的通孔时，将内层的焊盘信息施加到通孔穿过的每个内层。

公开(公告)号：US20080190658A1

公开(公告)日：2008-08-14

申请号：US12099957

申请日：2008-04-09

Applicant: Yukihiko TOYODA ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

Inventor： Yukihiko TOYODA ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.

Abstract translation: 本发明的目的是提供一种具有导体电路的布线距离短的多层印刷电路板，可广泛选择导体电路的设计，并且由于在层间树脂绝缘层中几乎不发生破裂 通孔附近。 本发明是一种多层印刷电路板，包括：导体电路和层间树脂绝缘层，其以交替的方式和重复地串联形成在基板上，其中通过层间树脂绝缘层的导体电路的连接通过通孔 孔，其中形成通孔中的不同级别的通孔，以形成堆叠通孔结构，并且其中不同层级中的上述通孔的平台直径中的至少一个具有 堆叠通孔结构不同于其它通孔的焊盘直径。

公开(公告)号：US20080179744A1

公开(公告)日：2008-07-31

申请号：US11739515

申请日：2007-04-24

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H01L23/48

CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

公开(公告)号：US20080066951A1

公开(公告)日：2008-03-20

申请号：US11978808

申请日：2007-10-30

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H05K1/02

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises a center segment distributing power and low-speed signaling, and outer segments for high-speed signaling. The segments use dielectric materials with different dielectric constants, with the outer segments supporting higher-speed signal transmission.

Abstract translation: 电路板包括分配功率和低速信号的中心段，以及用于高速信令的外部段。 这些段使用具有不同介电常数的介电材料，外部段支持更高速度的信号传输。