公开(公告)号：US20120125680A1

公开(公告)日：2012-05-24

申请号：US13357663

申请日：2012-01-25

Applicant: Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

Inventor： Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC: H05K1/02 ,  C25D5/02 ,  B23K1/20 ,  B23K31/02 ,  H05K3/46 ,  C25D7/00

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以防止通孔的连接的可靠性。 因此，可以提高通孔连接的可靠性。

公开(公告)号：US08153907B2

公开(公告)日：2012-04-10

申请号：US12010437

申请日：2008-01-24

Applicant: Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

Inventor： Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

IPC: H05K1/11

CPC classification number: H05K1/0236 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T428/12465

Abstract: An electromagnetic bandgap structure and a printed circuit board that solve a mixed signal problem are disclosed. In accordance with embodiments of the present invention, the electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, stacked in the first metal layer; a second metal layer, stacked in the first dielectric layer, and having a holed formed at a position of the second dielectric layer; a second dielectric layer, stacked in the second metal layer; a metal plate, stacked in the second dielectric layer; a first via, penetrating the hole formed in the second metal layer and connecting the first metal layer and the metal plate; a third dielectric layer, stacked in the metal plate and the second dielectric layer; a third metal layer, stacked in the third dielectric layer; and a second via, connecting the second metal layer to the third metal layer.

Abstract translation: 公开了一种解决混合信号问题的电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构包括第一金属层; 第一介电层，堆叠在第一金属层中; 第二金属层，堆叠在第一介电层中，并且具有形成在第二介电层的位置的孔; 第二介电层，堆叠在第二金属层中; 金属板，堆叠在第二介电层中; 穿过形成在第二金属层中的孔并连接第一金属层和金属板的第一通孔; 第三电介质层，堆叠在所述金属板和所述第二介电层中; 第三金属层，堆叠在第三介电层中; 以及将第二金属层连接到第三金属层的第二通孔。

公开(公告)号：US08129625B2

公开(公告)日：2012-03-06

申请号：US10551439

申请日：2004-04-06

Applicant: Shinobu Kato

Inventor： Shinobu Kato

IPC: H05K1/16

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09609 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a core substrate 30, a ground through hole 36E and a power through hole 36P are disposed in the grid formation, so that electromotive force induced in X direction and Y direction cancel out each other. As a result, even if mutual inductance is reduced and a high frequency IC chip is loaded, electric characteristic and reliability can be improved without generating malfunction or error.

Abstract translation: 在芯基板30中，在栅格形成中设置有接地贯通孔36E和电力通孔36P，使得在X方向和Y方向上感应的电动势相互抵消。 结果，即使减小互感并且加载高频IC芯片，也可以提高电特性和可靠性而不产生故障或错误。

公开(公告)号：US08116091B2

公开(公告)日：2012-02-14

申请号：US12873815

申请日：2010-09-01

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed circuit board has a core substrate including a resin substrate having an opening, a capacitor formed in the opening and having a first electrode structure having a portion facing to the upper surface of the core substrate and a second electrode structure having a portion facing to the lower surface of the core substrate, an upper insulating layer formed over the upper surface of the core substrate and having a conductive circuit formed over the upper insulating layer and a via hole electrically connecting the portion of the first electrode structure and the conductive circuit of the upper insulating layer, and a lower insulating layer formed over the lower surface of the core substrate and having a conductive circuit formed over the lower insulating layer and a via hole electrically connecting the portion of the second electrode structure and the conductive circuit of the lower insulating layer.

Abstract translation: 印刷电路板具有包括具有开口部的树脂基板的芯基板，形成在开口部的电容器，具有第一电极结构，具有与芯基板的上表面相对的部分，第二电极结构体具有面向 芯基板的下表面，形成在芯基板的上表面上方并具有形成在上绝缘层上的导电电路的上绝缘层和将第一电极结构的部分与导电电路电连接的通孔， 上绝缘层和下绝缘层，形成在芯基板的下表面上，并且具有形成在下绝缘层上的导电电路和将第二电极结构的部分与下部绝缘层的导电电路电连接的通孔 绝缘层。

公开(公告)号：US20120017437A1

公开(公告)日：2012-01-26

申请号：US13252256

申请日：2011-10-04

Applicant: Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

IPC: H05K3/40

CPC classification number: H05K1/0313 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/52 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/097 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0257 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0425 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

Abstract translation: 一种电路化基板，包括用于提供电连接的导电浆料。 在一个实施方案中，糊状物包括包含纳米颗粒的金属组分，并且可以包括附加元素，例如焊料或其它金属微粒，以及导电聚合物和有机物。 糊料组合物的颗粒烧结并且根据添加的另外的元素而熔化，因为层压，从而形成通过糊料的有效连续的电路。 还提供了制造这种基板的方法，以及利用该基板并且包括诸如与其耦合的半导体芯片的电子部件的电组件。

公开(公告)号：US20110289773A1

公开(公告)日：2011-12-01

申请号：US13209052

申请日：2011-08-12

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H05K3/30

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/188 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层，第二绝缘层和导电膜的基底基板的方法制造印刷线路板。 在基于对准标记确定的位置处将电子部件放置在第一绝缘层上。 在将电子部件封闭在第二绝缘层的开口内之后，在基于对准标记确定的位置处形成暴露电子部件的端子的通孔，该位置用于确定电子部件的位置。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US20110252639A1

公开(公告)日：2011-10-20

申请号：US13172974

申请日：2011-06-30

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K3/10

CPC classification number: H05K1/167 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09536 ,  H05K2201/09809 ,  H05K2203/1453 ,  Y10T29/49155 ,  Y10T29/49169

Abstract: A printed wiring board with a built-in resistive element comprising a first electrode formed on the surface of an insulating member, a second electrode provided adjacent to the first electrode to form a space therebetween, a resistor-filling part formed by the space between the first electrode and the second electrode, and a resistive element comprising a resistive material provided in the resistor-filling part wherein the resistor-filling part is substantially enclosed by the first electrode and the second electrode.

Abstract translation: 一种具有内置电阻元件的印刷电路板，包括形成在绝缘构件表面上的第一电极，与第一电极相邻设置以在其间形成空间的第二电极，由第一电极之间的空间形成的电阻器填充部分， 第一电极和第二电极，以及电阻元件，其包括设置在电阻器填充部分中的电阻材料，其中电阻器填充部分基本上被第一电极和第二电极包围。

公开(公告)号：US08024858B2

公开(公告)日：2011-09-27

申请号：US12351954

申请日：2009-01-12

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/188 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层，第二绝缘层和导电膜的基底基板的方法制造印刷线路板。 在基于对准标记确定的位置处将电子部件放置在第一绝缘层上。 在将电子部件封闭在第二绝缘层的开口内之后，在基于对准标记确定的位置处形成暴露电子部件的端子的通孔，该位置用于确定电子部件的位置。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US08013688B2

公开(公告)日：2011-09-06

申请号：US12854617

申请日：2010-08-11

Applicant: George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

Inventor： George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

IPC: H01P5/12 ,  H01P3/08

CPC classification number: H05K1/16 ,  H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P1/203 ,  H01P1/20381 ,  H01P1/2135 ,  H01P5/10 ,  H03H7/0115 ,  H03H7/075 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1775 ,  H03H7/38 ,  H03H7/42 ,  H03H7/463 ,  H03H2001/0085 ,  H05K1/024 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4644 ,  H05K3/4673 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/09536 ,  H01L2924/00

Abstract: The present invention provides all organic fully-packaged miniature bandpass filters, baluns, diplexers, multiplexers, couplers and a combination of the above manufactured using liquid crystalline polymer (LCP) and other multilayer polymer based substrates. These devices are manufactured using one or more LCP layers having integrated passive components formed thereon to provide the density and performance necessary for multi-band wireless devices. In the designs involving multiple LCP layers, the LCP layers are separated by prepeg layers. In accordance with an aspect of the present invention, coplanar waveguide, hybrid stripline/coplanar waveguide and/or microstrip topologies are utilized to form the integrated passive components, and the devices can be mass produced on large area panels at least 18 inches by 12 inches with line widths smaller than 10 um.

Abstract translation: 本发明提供了使用液晶聚合物（LCP）和其它多层聚合物基底板制造的所有有机全封装微型带通滤光器，平衡 - 不平衡转换器，双工器，多路复用器，耦合器和上述组合。 这些设备使用一个或多个LCP层制造，其中形成有集成的无源元件，以提供多频带无线设备所需的密度和性能。 在涉及多个LCP层的设计中，LCP层被预制层隔开。 根据本发明的一个方面，共面波导，混合带状线/共面波导和/或微带线拓扑被用于形成集成的无源部件，并且可以在大面积的面板上批量生产至少18英寸×12英寸 线宽小于10um。

公开(公告)号：US07979983B2

公开(公告)日：2011-07-19

申请号：US11696670

申请日：2007-04-04

Applicant: Steven C. Bird ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

Inventor： Steven C. Bird ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

IPC: H01K3/10 ,  H05K1/11

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

Abstract translation: 提供了用于优化专用集成电路（ASIC）和对应于高密度互连（HDI）印刷电路板（PCB）布局）的其他IC引脚分配的技术。 应用本文描述的技术，可以系统地和策略性地规划引脚分配，例如，为了减少PCB层数量和相关成本，增加信号完整性和速度，减少由ASIC及其支持电路使用的表面积， 与安装在多层PCB上的ASIC的传统设计相比，减少了平面穿孔，并减少了串扰。