公开(公告)号：US20010040272A1

公开(公告)日：2001-11-15

申请号：US09848801

申请日：2001-05-04

Inventor： Naohiro Mashino

IPC: H01L029/00 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L23/642 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/141 ,  H05K1/162 ,  H05K3/42 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer comprises: a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor comprises first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract translation: 适于在安装板和要安装在安装板上的半导体芯片之间使用的插入器。 插入件包括：具有第一和第二表面的耐热绝缘体，所述绝缘体设置有在所述第一表面和所述第二表面处开口的多个通孔; 通过设置在至少一个通孔的内壁上的导体彼此电连接的绝缘体的第一和第二表面上形成的布线图案; 和电容器。 电容器包括形成在绝缘体上的第一电极，并且具有形成在至少一个其它通孔的内壁上的连接部分，形成在第一电极上的电介质层和形成在电介质层上的第二电极。

公开(公告)号：US5920454A

公开(公告)日：1999-07-06

申请号：US798650

申请日：1997-02-11

Applicant: Kazuo Nomura ,  Nobutsugu Nakanuma ,  Ichiro Ishiyama ,  Koji Higashi ,  Masaki Kato ,  Ichiro Nagare ,  Hiroyuki Kurokawa ,  Yozo Ohara

Inventor： Kazuo Nomura ,  Nobutsugu Nakanuma ,  Ichiro Ishiyama ,  Koji Higashi ,  Masaki Kato ,  Ichiro Nagare ,  Hiroyuki Kurokawa ,  Yozo Ohara

IPC: H05K1/16 ,  H05K1/18 ,  H01K4/06 ,  H01K4/002

CPC classification number: H05K1/162 ,  H05K1/183 ,  H05K2201/0209 ,  H05K2201/09763

Abstract: A printed capacitor-mounted circuit board capable of increasing a capacity of each of printed capacitors formed on a printed board. A copper-clad laminate is arranged so as to act as an insulating substrate. The printed capacitors each include a first electrode made of a copper foil and arranged on a front surface of the copper-clad laminate. Then, a dielectric layer made of a dielectric paste is arranged on the first electrode and a second electrode made of a conductive paint is arranged on the dielectric layer.

Abstract translation: 一种印刷电容器安装的电路板，其能够增加形成在印刷电路板上的每个印刷电容器的容量。 覆铜层压板被布置成用作绝缘基板。 印刷电容器各自包括由铜箔制成的第一电极并布置在覆铜层压板的前表面上。 然后，在第一电极上布置由电介质浆料构成的电介质层，并且在电介质层上设置由导电涂料制成的第二电极。

公开(公告)号：US5917229A

公开(公告)日：1999-06-29

申请号：US688241

申请日：1996-07-29

Applicant: Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

Inventor： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

IPC: G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L29/00

CPC classification number: H05K7/1092 ,  G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  G01R1/06 ,  G01R31/2863 ,  H01L2924/0002 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for interconnecting the terminals of electronic components mounted on printed circuit boards (PCBs), multichip modules (MCMs) or in integrated circuit packages (IC packages). Both types of programmable elements can be fabricated as part of the regular processes used to fabricate PCBs, MCMs, or IC package (pin grid array). For fuses and antifuses, the material, geometry and dimensions can be varied to minimize the real estate and maximize programming efficiency (reduce programming time). Each type of programmable element, fuse or antifuse, can be separately used in matrices to form programmable board and package substrates. When both types of programmable elements are used together, more efficient placement and route architectures take advantage of the characteristics of each type of programmable element. Furthermore, combinations of both fuses and antifuses in the same structure allows the architecture to be reprogrammable. Fuse and antifuses can be easily used to form programmable burn-in boards and field programmable smart cards, credit cards, sockets and cable connectors.

Abstract translation: 公开了两种类型的可编程元件，熔丝和反熔丝，用于互连安装在印刷电路板（PCB），多芯片模块（MCM）或集成电路封装（IC封装）中的电子部件的端子。 可以将两种类型的可编程元件制造为用于制造PCB，MCM或IC封装（引脚栅阵列）的常规工艺的一部分。 对于保险丝和反熔丝，可以改变材料，几何形状和尺寸以最小化房地产并最大化编程效率（减少编程时间）。 每种类型的可编程元件，熔丝或反熔丝可以单独用于矩阵中，以形成可编程的板和封装衬底。 当两种类型的可编程元件一起使用时，更有效的布局和布线架构可以利用每种可编程元件的特性。 此外，在相同结构中的熔丝和反熔丝的组合允许架构可重新编程。 保险丝和反熔丝可以轻松地用于形成可编程的老化板和现场可编程智能卡，信用卡，插座和电缆连接器。

公开(公告)号：US5834824A

公开(公告)日：1998-11-10

申请号：US405259

申请日：1995-03-14

Applicant: William H. Shepherd ,  Steve S. Chiang ,  John Y. Xie

Inventor： William H. Shepherd ,  Steve S. Chiang ,  John Y. Xie

IPC: G01R1/04 ,  G01R1/06 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L27/02

CPC classification number: H05K7/1092 ,  G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5252 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  G01R1/06 ,  H01L2924/0002 ,  H01R23/70 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: A novel antifuse includes a composite of conductive particles dispersed throughout a nonconductive matrix, which composite is located inside an antifuse via. The antifuse via is defined by a dielectric layer that separates two electrodes. The electrodes can be located in the same conductive layer plane (typically parallel to and isolated from one another) or in two different conductive planes (typically formed transverse to one another and separated by a dielectric with an antifuse via formed therein). The electrodes can be coupled to, for example, active or passive regions of the integrated circuit. One embodiment of an antifuse (also called "composite antifuse") has only the composite in an antifuse via between the two conductive layers. Another embodiment of an antifuse (also called "hybrid antifuse") includes in addition to the composite, one or more thin dielectric layers also located in the antifuse via between the two conductive layers.

Abstract translation: 一种新颖的反熔丝包括分散在整个非导电基质中的导电颗粒的复合物，该复合材料位于反熔丝通孔内部。 反熔丝通孔由分离两个电极的电介质层限定。 电极可以位于相同的导电层平面（通常彼此平行并彼此隔离）或两个不同的导电平面（通常形成为彼此横向并由其中形成有反熔丝通孔的电介质隔开）。 电极可以耦合到例如集成电路的有源或无源区域。 反熔丝（也称为“复合反熔丝”）的一个实施例仅在两个导电层之间的反熔丝通孔中具有复合材料。 反熔丝（也称为“混合反熔丝”）的另一实施例除了复合材料之外还包括一个或多个薄介电层，其也位于两个导电层之间的反熔丝中。

公开(公告)号：US5537108A

公开(公告)日：1996-07-16

申请号：US319851

申请日：1994-10-07

Applicant: Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu

Inventor： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu

IPC: G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H04Q1/18

CPC classification number: G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: A programming method in accordance with this invention partitions traces of a fuse matrix into groups wherein each group contains traces connected to fuses that are to remain intact. All of the traces in a group are connected to a first voltage so that the fuses between traces in the group are subjected to minimal currents. In one embodiment, all of the traces that are not in the group connected to the first voltage are connected to a second voltage such that a programming current passes through fuses to be programmed. In an alternative embodiment, traces in a second group are connected to the second voltage and all of the remaining traces are shorted to each other.

Abstract translation: 根据本发明的编程方法将熔丝矩阵的迹线分成组，其中每组包含连接到保持完整的熔丝的迹线。 组中的所有迹线都连接到第一电压，使得组中迹线之间的熔丝经受最小电流。 在一个实施例中，不在连接到第一电压的组中的所有迹线被连接到第二电压，使得编程电流通过待编程的熔丝。 在替代实施例中，第二组中的迹线连接到第二电压，并且所有剩余的迹线彼此短接。

公开(公告)号：US4737747A

公开(公告)日：1988-04-12

申请号：US880987

申请日：1986-07-01

Applicant: James M. Henderson ,  Terry L. Gibbs

Inventor： James M. Henderson ,  Terry L. Gibbs

IPC: H01P1/22 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46 ,  H01P1/00 ,  H01P1/26

CPC classification number: H01P1/227 ,  H05K1/167 ,  H05K1/0237 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K2201/09763 ,  H05K2203/0361 ,  H05K3/4611 ,  Y10T29/49082

Abstract: A resistive element is formed on a printed circuit board using only printed circuit board fabrication techniques. Two printed circuit board strata are laminated together into a multi-layer printed circuit board. A desired trace pattern is etched into a first layer of a first stratum that has first and second conductive metallic layers clad to opposing sides of a first dielectric substrate. A bi-metallic clad substrate having a resistive layer clad to a first side of a second dielectric substrate, a third conductive layer clad to the resistive layer, and a fourth conductive layer clad to a second side of the second dielectric substrate represents the second stratum. The third conductive layer is etched to leave only pads. The resistive layer is etched to form resistive elements of desired resistivity between the pads. When the two strata are laminated together, the pads couple to the trace pattern at desired locations.

Abstract translation: 电阻元件仅使用印刷电路板制造技术形成在印刷电路板上。 两个印刷电路板层叠在一起成为多层印刷电路板。 将期望的迹线图案蚀刻到第一层的第一层中，该第一层具有包覆到第一介电衬底的相对侧的第一和第二导电金属层。 一种双金属包覆基板，其具有包覆到第二电介质基板的第一侧的电阻层，包覆到所述电阻层的第三导电层，以及包覆到所述第二电介质基板的第二侧的第四导电层， 。 蚀刻第三导电层以仅留下焊盘。 电阻层被蚀刻以形成垫之间所需电阻率的电阻元件。 当两个层叠在一起时，垫在期望的位置耦合到迹线图案。

公开(公告)号：US09924597B2

公开(公告)日：2018-03-20

申请号：US15111305

申请日：2015-02-20

Applicant: MITSUI MINING & SMELTING CO., LTD.

Inventor： Fujio Kuwako ,  Toshifumi Matsushima ,  Toshihiro Hosoi

IPC: H05K1/09 ,  H05K1/16 ,  B32B15/00 ,  B32B15/04 ,  B32B15/20 ,  H05K3/02 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/162 ,  B32B15/00 ,  B32B15/04 ,  B32B15/20 ,  B32B2307/51 ,  B32B2457/00 ,  B32B2457/08 ,  B32B2457/16 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/022 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2201/09763

Abstract: A material for forming of the capacitor layer which generates no crack in drilling on the dielectric layer of the capacitor in manufacturing of a highly multilayered printed wiring board embedded a capacitor circuit. Copper clad laminate for forming of an embedded capacitor layer of a multilayered printed wiring board including an embedded capacitor circuit having a layer structure of copper layer/dielectric layer of the capacitor/copper layer in an inner layer characterized in that the composite elastic modulus Er of the resin film constituting the dielectric layer of the capacitor along the thickness direction is less than 6.1 GPa is employed.

公开(公告)号：US09648749B1

公开(公告)日：2017-05-09

申请号：US14943299

申请日：2015-11-17

Applicant: Martin Brokner Christiansen ,  Leonard George Chorosinski ,  H. Craig Heffner ,  Stanley Katsuyoshi Wakamiya ,  Keith R. Kirkwood

Inventor： Martin Brokner Christiansen ,  Leonard George Chorosinski ,  H. Craig Heffner ,  Stanley Katsuyoshi Wakamiya ,  Keith R. Kirkwood

IPC: H05K1/00 ,  H05K1/18 ,  H05K1/02 ,  H05K1/03 ,  H05K3/46 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/181 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/303 ,  H05K3/46 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/09063 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09763

Abstract: A circuit card assembly includes a substrate having longitudinally spaced first and second substrate end edges and transversely spaced top and bottom substrate surfaces. The top and/or bottom substrate surface has first, second, and third substrate regions. The first substrate region is directly laterally adjacent the first substrate side edge. The third substrate region is directly laterally adjacent the second substrate side edge. The second substrate region is located between the first and third substrate regions. At least one circuit trace is located on the selected substrate surface. The portion of the circuit trace in the first substrate region is made of only a first material. The portion of the circuit trace in the third substrate region is made of only a second material. The portion of the circuit trace in the second substrate region is made of both the first and second materials.

公开(公告)号：US20150009438A1

公开(公告)日：2015-01-08

申请号：US14113582

申请日：2013-07-31

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD.

Inventor： Peng Du ,  Ming hung Shih ,  Jiali Jiang

IPC: H05K1/02 ,  G02F1/1362

CPC classification number: H05K1/025 ,  G02F1/1345 ,  H05K1/0248 ,  H05K1/162 ,  H05K2201/0326 ,  H05K2201/0391 ,  H05K2201/09227 ,  H05K2201/09763 ,  H05K2201/10136

Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

Abstract translation: 阵列基板的扇出线结构包括布置在阵列基板的扇出区域上的第一扇出线和布置在阵列基板的扇出区域上的第二扇出线。 第二导电膜布置在第二扇出线的底部，第二电容器形成在第二导电膜和第二扇出线的第一导电膜之间，第二电容用于降低扇出线之间的阻抗差 。 第二电容器的电容值取决于第二导电膜和第一导电膜之间的重叠面积。

公开(公告)号：US08715839B2

公开(公告)日：2014-05-06

申请号：US11479159

申请日：2006-06-30

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: B32B9/00 ,  B32B19/00 ,  H01L27/108 ,  H01L29/94 ,  H01C10/10 ,  H01F5/00

CPC classification number: H01Q9/0414 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q15/0086 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T428/12493

Abstract: An electrical component provides a ceramic element located on or in a dielectric substrate between and in contact with a pair of electrical conductors, wherein the ceramic element includes one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.5 mol % throughout the ceramic element. A method of fabricating an electrical component, provides or forming a ceramic element between and in contact with a pair of electrical conductors on a substrate including depositing a mixture of metalorganic precursors and causing simultaneous decomposition of the metal oxide precursors to form the ceramic element including one or more metal oxides.

Abstract translation: 电气部件提供位于电介质基板上或介质基板之间的陶瓷元件，其与一对电导体接触并接触，其中陶瓷元件包括一种或多种具有小于或等于1.5摩尔的金属 - 氧化物组成均匀性波动的金属氧化物 ％整个陶瓷元件。 一种制造电气部件的方法，在衬底上提供或形成与一对电导体接触的陶瓷元件，包括沉积金属有机前体的混合物并引起金属氧化物前体的同时分解以形成陶瓷元件，包括一个 或更多的金属氧化物。