公开(公告)号：US20150008498A1

公开(公告)日：2015-01-08

申请号：US14330847

申请日：2014-07-14

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

IPC: H01L27/07 ,  H01L21/321 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L27/0733 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/32105 ,  H01L21/743 ,  H01L21/823437 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/945

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract translation: 半导体元件布置方法包括产生沟槽晶体管结构，其包括设置在半导体本体中的至少一个沟槽和设置在至少一个沟槽中的至少一个栅电极。 该方法还包括制造电容器结构，其包括设置在至少一个另外的沟槽中的电极结构，所述电极结构包括至少一个电极。 电极结构的栅电极和至少一个电极通过常规工艺步骤制造。

公开(公告)号：US20140209905A1

公开(公告)日：2014-07-31

申请号：US13754240

申请日：2013-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Steffen Thiele

IPC: H01L23/544 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit including a semiconductor device has a power component including a plurality of trenches in a cell array, the plurality of trenches running in a first direction, and a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component. The integrated circuit further includes isolation trenches disposed between the sensor component and the power component, an insulating material being disposed in the isolation trenches. The isolation trenches run in a second direction that is different from the first direction.

Abstract translation: 包括半导体器件的集成电路具有包括单元阵列中的多个沟槽的功率分量，沿第一方向运行的多个沟槽和集成到功率组件的单元阵列中的传感器组件，并且包括具有 小于电力部件的电池阵列的面积的区域。 集成电路还包括设置在传感器部件和功率部件之间的隔离沟槽，绝缘材料设置在隔离沟槽中。 隔离沟槽沿与第一方向不同的第二方向延伸。

公开(公告)号：US12136670B2

公开(公告)日：2024-11-05

申请号：US17824198

申请日：2022-05-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L21/74 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/40

Abstract: A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side.

公开(公告)号：US11695069B2

公开(公告)日：2023-07-04

申请号：US17316067

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4232

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

公开(公告)号：US11018250B2

公开(公告)日：2021-05-25

申请号：US16404005

申请日：2019-05-06

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

公开(公告)号：US20200135564A1

公开(公告)日：2020-04-30

申请号：US16176403

申请日：2018-10-31

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Christian Westermeier ,  Jochen Hilsenbeck ,  Jens Peter Konrath ,  Boris Mayerhofer ,  Anatoly Sotnikov

IPC: H01L21/78 ,  H01L21/04 ,  H01L29/16

Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.

公开(公告)号：US20190157449A1

公开(公告)日：2019-05-23

申请号：US16235550

申请日：2018-12-28

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L29/78 ,  H01L23/48 ,  H01L27/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L21/74 ,  H01L29/66 ,  H01L29/45 ,  H01L29/861 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor body includes a first side and a second side opposite to the first side, a first dielectric disposed on the first side, a second dielectric disposed on the second side, one or more FET devices disposed at the first side, a first contact trench extending through the first dielectric at the first side, a first conductive material disposed in the first contact trench and electrically connected to the semiconductor body, a second contact trench extending through the second dielectric and into the semiconductor body at the second side, and a second conductive material disposed in the second contact trench and electrically connected to the semiconductor body at sidewalls of the second contact trench.

公开(公告)号：US20190109226A1

公开(公告)日：2019-04-11

申请号：US16201081

申请日：2018-11-27

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Dietrich Bonart ,  Ludger Borucki

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/739 ,  H01L29/08 ,  H01L29/06 ,  H01L23/051 ,  H02J7/24 ,  H01L29/10 ,  H01L23/24 ,  H02J7/14 ,  H01L29/861

Abstract: An alternator assembly includes an input terminal configured to input an alternating voltage, an output terminal configured to output a rectified voltage, and a gated diode arranged in a load path between the input terminal and the output terminal.

公开(公告)号：US09865792B2

公开(公告)日：2018-01-09

申请号：US14282886

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Donald Dibra ,  Christoph Kadow ,  Markus Zundel

IPC: G01K7/04 ,  H01L35/32 ,  G01K1/08 ,  G01K7/02

CPC classification number: H01L35/32 ,  G01K1/08 ,  G01K7/02

Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.

公开(公告)号：US09806188B2

公开(公告)日：2017-10-31

申请号：US15173337

申请日：2016-06-03

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L21/768 ,  H01L21/28 ,  H01L23/48 ,  H01L21/74 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/28008 ,  H01L21/28229 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. In a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. The oxide layer is removed from the first trench completely or at least partly such that the semiconductor body has an exposed first surface area arranged in the first trench. An electrically conductive material is filled into the second trench, and the semiconductor body and the oxide layer are partially removed such that the electrically conductive material has an exposed second surface area at the bottom side.