公开(公告)号：US20220293509A1

公开(公告)日：2022-09-15

申请号：US17197531

申请日：2021-03-10

Applicant: Intel Corporation

Inventor： Rahul Manepalli ,  Suddhasattwa Nad ,  Marcel Wall ,  Darko Grujicic

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace.

公开(公告)号：US11445616B2

公开(公告)日：2022-09-13

申请号：US15954040

申请日：2018-04-16

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Rahul Manepalli ,  Marcel Wall

IPC: H05K3/38 ,  H01L21/027 ,  H01L21/48 ,  H05K1/03 ,  H01L23/498 ,  H01L23/00

Abstract: Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.

公开(公告)号：US11116084B2

公开(公告)日：2021-09-07

申请号：US16634804

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US20250125307A1

公开(公告)日：2025-04-17

申请号：US18985540

申请日：2024-12-18

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Jason M. Gamba ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Xiaoxuan Sun ,  Omkar G. Karhade ,  Xavier Francois Brun ,  Yonggang Li ,  Suddhasattwa Nad ,  Bohan Shan ,  Haobo Chen ,  Gang Duan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

公开(公告)号：US20250105222A1

公开(公告)日：2025-03-27

申请号：US18475326

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Gang Duan ,  Yosuke Kanaoka ,  Minglu Liu ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bohan Shan ,  Haobo Chen ,  Benjamin T. Duong ,  Jeremy Ecton ,  Suddhasattwa Nad

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways through the RDL, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the RDL and by interconnects.

公开(公告)号：US20240332322A1

公开(公告)日：2024-10-03

申请号：US18129407

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Kripa Chauhan

IPC: H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66 ,  H01L29/772

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66409 ,  H01L29/772

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an electronic package substrate including a glass core layer and a regulator circuit. A first portion of the circuit components of the regulator circuit is embedded in the glass core layer and a second portion of the circuit components of the regulator circuit is formed on a surface of the glass core layer.

公开(公告)号：US20240327201A1

公开(公告)日：2024-10-03

申请号：US18192576

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Mohammad Mamunur Rahman ,  Suddhasattwa Nad ,  Sashi Kandanur ,  Darko Grujicic ,  Benjamin Duong ,  Srinivas Pietambaram ,  Tarek Ibrahim ,  Whitney Bryks

IPC: B81B7/00 ,  B81C1/00 ,  G02B6/12

CPC classification number: B81B7/0048 ,  B81C1/00325 ,  G02B6/12004 ,  B81B2201/0228 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2201/03 ,  B81B2201/045 ,  B81B2207/07 ,  B81B2207/096 ,  B81B2207/097

Abstract: MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.

公开(公告)号：US20240219633A1

公开(公告)日：2024-07-04

申请号：US18090258

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: G02B6/122 ,  G02B6/138

CPC classification number: G02B6/1221 ,  G02B6/138 ,  G02B2006/12038

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240219632A1

公开(公告)日：2024-07-04

申请号：US18091535

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Umesh Prasad ,  Suddhasattwa Nad ,  Benjamin T. Duong ,  Yi Yang

IPC: G02B6/122 ,  G02B1/02 ,  G02B3/00

CPC classification number: G02B6/122 ,  G02B1/02 ,  G02B3/0087 ,  G02B2006/12061

Abstract: Technologies for integrated graded index (GRIN) lenses for photonic circuits is disclosed. In one illustrative embodiment, a glass substrate has a cavity in which a GRIN lens is disposed. In other embodiments, the GRIN lens may be on a surface of the glass substrate. The GRIN lens focuses and collimates light to a free-space beam from a waveguide defined in the glass substrate. Another component such as a photonic integrated circuit (PIC) die may also have a GRIN lens and focus the free-space beam into a waveguide in the PIC die. The use of GRIN lenses allows for passive coupling to waveguides without further active alignment that minimizes signal transmission losses.

公开(公告)号：US20240213235A1

公开(公告)日：2024-06-27

申请号：US18089459

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1427 ,  H01L2924/1431

Abstract: An apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. Other embodiments are also disclosed and claimed.