公开(公告)号：US06855738B2

公开(公告)日：2005-02-15

申请号：US10456127

申请日：2003-06-06

Applicant: Ludovic L. Valette ,  Catherine Marestin ,  Regis Mercier

Inventor： Ludovic L. Valette ,  Catherine Marestin ,  Regis Mercier

IPC: B32B27/04 ,  C08G59/14 ,  C08G59/18 ,  C08J9/26 ,  H05K1/03 ,  H05K3/00 ,  C08J9/00

CPC classification number: B32B15/08 ,  B32B27/04 ,  B32B2457/00 ,  B82Y30/00 ,  C08G59/1433 ,  C08G59/1438 ,  C08G59/18 ,  H05K1/0313 ,  H05K3/0011 ,  H05K2201/0116 ,  H05K2203/1105 ,  Y10S428/901 ,  Y10T428/24994 ,  Y10T428/24998 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31518 ,  Y10T428/31522 ,  Y10T428/31525 ,  Y10T428/31529

Abstract: A process of making a nanoporous substrate, such as the matrix in an electrical laminate, by grafting onto an organic resin backbone a thermolabile functionality by reacting hydrogen active groups of the organic resin with a compound containing thermolabile groups; then thermally degrading the thermolabile groups grafted on the organic resin to form a nanoporous laminate. Advantageously, the nanoporous electrical laminate has a low dielectric constant (Dk) because of the nanopores present in the laminate matrix.

Abstract translation: 通过使有机树脂的氢活性基团与含有不耐热基团的化合物反应，通过将有机树脂主链上的可活化的官能团接枝到有机树脂主链上来制备纳米多孔基材，例如电气层压板中的基体的方法; 然后热降解接枝在有机树脂上的热不稳定基团以形成纳米多孔层压体。 有利地，纳米多孔电性层压体由于纳米孔存在于层叠基质中而具有低介电常数（Dk）。

公开(公告)号：US06835889B2

公开(公告)日：2004-12-28

申请号：US10251825

申请日：2002-09-23

Applicant: Toshiro Hiraoka ,  Yasuyuki Hotta ,  Koji Asakawa ,  Shigeru Matake

Inventor： Toshiro Hiraoka ,  Yasuyuki Hotta ,  Koji Asakawa ,  Shigeru Matake

IPC: H01L2329

CPC classification number: H05K3/423 ,  H01C7/00 ,  H01F17/0006 ,  H01F41/041 ,  H01F2017/006 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0116 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/1545

Abstract: The present invention provides a composite material such as a passive element, a passive element composite component, a substrate with a built-in passive element and a composite wiring substrate which are free from, for example, a layer peeling problem and enables high density packaging with ease. In the present invention, a porous base material is divided into plural functional regions and a material having different electromagnetic characteristics is filled in a pore of the porous base material of each functional region, to form a passive element or a wiring substrate. Among the aforementioned plural functional regions, at least one functional region is a conductive material region filled with a conductive material and other regions are filled with a high-dielectric material, a high-permeability material or a low-dielectric material. This structure ensures that a single passive element, plural passive elements or a wiring substrate provided with a circuit wiring can be formed on a porous base material efficiently.

Abstract translation: 本发明提供了诸如无源元件，无源元件复合元件，具有内置无源元件的基板和复合布线基板的复合材料，其不含例如层剥离问题并且能够实现高密度封装 轻松。 在本发明中，将多孔基材分成多个功能区域，并且将具有不同电磁特性的材料填充在各功能区域的多孔基材的孔中，形成无源元件或布线基板。 在上述多个功能区域中，至少一个功能区域是填充有导电材料的导电材料区域，并且其它区域填充有高介电材料，高磁导率材料或低电介质材料。 这种结构确保了能够有效地在多孔基材上形成单个无源元件，多个无源元件或设置有电路布线的布线基板。

公开(公告)号：US20040247880A1

公开(公告)日：2004-12-09

申请号：US10456127

申请日：2003-06-06

Inventor： Ludovic L. Valette ,  Catherine Marestin ,  Regis Mercier

IPC: B32B027/38 ,  B32B005/18 ,  C08L063/00

CPC classification number: B32B15/08 ,  B32B27/04 ,  B32B2457/00 ,  B82Y30/00 ,  C08G59/1433 ,  C08G59/1438 ,  C08G59/18 ,  H05K1/0313 ,  H05K3/0011 ,  H05K2201/0116 ,  H05K2203/1105 ,  Y10S428/901 ,  Y10T428/24994 ,  Y10T428/24998 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31518 ,  Y10T428/31522 ,  Y10T428/31525 ,  Y10T428/31529

Abstract: A process of making a nanoporous substrate, such as the matrix in an electrical laminate, by grafting onto an organic resin backbone a thermolabile functionality by reacting hydrogen active groups of the organic resin with a compound containing thermolabile groups; then thermally degrading the thermolabile groups grafted on the organic resin to form a nanoporous laminate. Advantageously, the nanoporous electrical laminate has a low dielectric constant (Dk) because of the nanopores present in the laminate matrix.

Abstract translation: 通过使有机树脂的氢活性基团与含有不耐热基团的化合物反应，通过将有机树脂主链上的可活化的官能团接枝到有机树脂主链上来制备纳米多孔基材，例如电气层压板中的基体的方法; 然后热降解接枝在有机树脂上的热不稳定基团以形成纳米多孔层压体。 有利地，纳米多孔电性层压体由于纳米孔存在于层叠基质中而具有低介电常数（Dk）。

公开(公告)号：US20040187305A1

公开(公告)日：2004-09-30

申请号：US10820417

申请日：2004-04-07

Inventor： Toshiyuki Kawashima ,  Nobuharu Tahara ,  Kenichi Ikeda

IPC: B32B003/00

CPC classification number: H05K3/4655 ,  B32B5/18 ,  B32B7/04 ,  B32B38/08 ,  B32B2305/026 ,  B32B2379/08 ,  B32B2398/10 ,  B32B2457/08 ,  H05K3/4652 ,  H05K2201/0116 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2203/066 ,  H05K2203/1147 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T428/249953 ,  Y10T428/24997 ,  Y10T428/249982

Abstract: The present invention provides a method of manufacturing a wiring board, including the steps of preparing a composite sheet having an adherent sheet containing a thermosetting resin adhered to a porous film or impregnated with at least a part thereof, laminating at least the composite sheet on a wiring layer having a wiring pattern formed on an insulating layer, and heating and pressurizing the laminated product thus obtained or heating and pressurizing it after the pressurization to integrate the laminated product.

Abstract translation: 本发明提供了一种制造布线板的方法，包括以下步骤：制备具有附着在多孔膜上或浸渍有至少一部分的热固性树脂的粘合片的复合片，至少将该复合片层压在 布线层，其具有形成在绝缘层上的布线图案，并对由此获得的叠层产品进行加热和加压，或者在加压之后对其进行加压和加压以整合层压产品。

公开(公告)号：US20040183094A1

公开(公告)日：2004-09-23

申请号：US10768836

申请日：2004-01-29

Applicant: International Business Machines Corporation

Inventor： David Vincent Caletka ,  Krishna Darbha ,  Donald W. Henderson ,  Lawrence P. Lehman ,  George Henry Thiel

IPC: H01L031/111 ,  H01L029/74

CPC classification number: H01L23/49811 ,  B23K3/0623 ,  B23K2101/40 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05551 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15787 ,  H05K1/113 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0116 ,  H05K2201/0133 ,  H05K2201/0382 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49171 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05552

Abstract: Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.

公开(公告)号：US20040161922A1

公开(公告)日：2004-08-19

申请号：US10782657

申请日：2004-02-19

Applicant: Shipley Company, L.L.C.

Inventor： Michael K. Gallagher ,  Yujian You

IPC: H01L021/4763

CPC classification number: H01L21/02137 ,  B29C67/202 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/31695 ,  H01L21/481 ,  H01L21/7682 ,  H01L2221/1047 ,  H05K1/024 ,  H05K2201/0116 ,  Y10T428/24331

Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.

Abstract translation: 公开了制造电子装置，特别是集成电路的方法。 这种方法包括使用通过使用可去除的致孔剂材料制备的低介电常数材料。

公开(公告)号：US06774316B1

公开(公告)日：2004-08-10

申请号：US09890145

申请日：2001-07-26

Applicant: Takeshi Suzuki ,  Tatsuo Ogawa ,  Satoru Tomekawa ,  Yoshihiro Bessho ,  Tousaku Nishiyama ,  Tetsuyoshi Ogura

Inventor： Takeshi Suzuki ,  Tatsuo Ogawa ,  Satoru Tomekawa ,  Yoshihiro Bessho ,  Tousaku Nishiyama ,  Tetsuyoshi Ogura

IPC: H01R1204

CPC classification number: H05K3/462 ,  H05K1/0373 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0116 ,  H05K2201/0212 ,  H05K2201/0355 ,  H05K2201/10378 ,  H05K2203/1461 ,  Y10T29/49165

Abstract: The present invention aims to provide a wiring substrate highly reliable in insulation and connection and a method for manufacturing the wiring substrate. A wiring substrate having two or more wiring layers, insulation layers interposed between the neighboring wiring layers and containing an organic resin, and a via formed in the insulation layers and extended between neighboring wiring layers. The via including functional substances, as well as some of the voids (first voids) where at least the organic resins from the insulation layers exist and the remaining voids (second voids) where a gas exists.

Abstract translation: 本发明的目的在于提供一种绝缘和连接高度可靠的布线基板和布线基板的制造方法。 具有两层以上布线层的布线基板，位于相邻配线层之间并含有有机树脂的绝缘层，以及形成在绝缘层中并在相邻布线层之间延伸的通孔。 通孔包括功能性物质，以及至少存在绝缘层的有机树脂和存在气体的剩余空隙（第二空隙）的一些空隙（第一空隙）。

公开(公告)号：US06745464B2

公开(公告)日：2004-06-08

申请号：US10401607

申请日：2003-03-31

Applicant: Fumio Echigo ,  Hideki Higashitani ,  Daizo Andoh ,  Noritake Fukuda ,  Yasuhiro Nakatani ,  Tadashi Nakamura

Inventor： Fumio Echigo ,  Hideki Higashitani ,  Daizo Andoh ,  Noritake Fukuda ,  Yasuhiro Nakatani ,  Tadashi Nakamura

IPC: H01K310

CPC classification number: H05K3/4069 ,  H05K3/0032 ,  H05K3/20 ,  H05K3/386 ,  H05K2201/0112 ,  H05K2201/0116 ,  H05K2201/0355 ,  H05K2203/0191 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49172

Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.

Abstract translation: 通过施加和干燥包括紫外线吸收剂的树脂清漆304在具有粘合剂层302的基板的两侧上形成可移除掩模膜303，并且通过使用第三谐波YAG固体激光器形成细小通孔306 具有比紫外线范围内的波长相对较短波长的光可以减少通过层压方法形成可去除掩模膜的这种残留应变的效果以及更细孔钻孔 与使用具有较长波长的二氧化碳气体激光器的常规实施例相比可以进行。

公开(公告)号：US06703565B1

公开(公告)日：2004-03-09

申请号：US09686220

申请日：2000-10-11

Applicant: Masahide Tsukamoto ,  Masanaru Hasegawa ,  Hideo Hatanaka

Inventor： Masahide Tsukamoto ,  Masanaru Hasegawa ,  Hideo Hatanaka

IPC: H05K102

CPC classification number: H05K3/462 ,  H05K3/205 ,  H05K3/207 ,  H05K3/4069 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0116 ,  H05K2201/0376 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/1461 ,  Y10S156/923 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T156/1168

Abstract: A printed wiring board includes at least one insulator sheet having through holes filled with conductive material and a conductive wiring pattern. The wiring pattern is embedded in the insulator sheet so that an upper surface of the wiring pattern and surrounding portions of the insulator sheet form a flat surface. The insulator sheet may be made from a glass-epoxy prepreg or of a polyester or polyimide sheet coated with an adhesive or glue. The wiring pattern can be transferred to the insulator sheet from a surface of a releasable supporting sheet.

Abstract translation: 印刷电路板包括至少一个具有填充有导电材料的通孔和导电布线图案的绝缘片。 布线图案嵌入在绝缘片中，使得布线图案的上表面和绝缘片的周围部分形成平坦表面。 绝缘片可由玻璃环氧树脂预浸料或涂有粘合剂或胶水的聚酯或聚酰亚胺片制成。 布线图案可以从可释放的支撑片的表面转移到绝缘片。

公开(公告)号：US06697261B2

公开(公告)日：2004-02-24

申请号：US09749505

申请日：2000-12-28

Applicant: Shinji Matsuda

Inventor： Shinji Matsuda

IPC: H05K712

CPC classification number: H01L23/49833 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/09063 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: Conductive or solder bumps are stacked between a mounted component such as a BGA device and a printed wiring substrate in a multileveled printed circuit board unit. An interposer or relay substrate is interposed between the adjacent stacked conductive bumps. The interposer substrate is made of a porous material. When any difference in the expansion is caused between the printed wiring substrate and the mounted component, one side of the interposer substrate receives a relatively smaller displacement force while the other side of the interposer substrate receives a relatively larger displacement force. A shearing stress is induced in the interposer substrate. Deformation of the porous material serves to absorb the shearing stress in the interposer substrate. The conductive bumps bonded on one side of the interposer substrate as well as the conductive bumps bonded on the other side of the interposer substrate may be relieved from a shearing stress. Accordingly, the durability of the conductive bumps can be improved. The conductive bumps are allowed to keep a stronger bonding in a longer duration.