公开(公告)号：US20090184778A1

公开(公告)日：2009-07-23

申请号：US12354488

申请日：2009-01-15

Applicant: Kwang-Soo Park ,  Byoung-Ha Oh ,  Yong-Ho Ko

Inventor： Kwang-Soo Park ,  Byoung-Ha Oh ,  Yong-Ho Ko

IPC: H04B15/00

CPC classification number: H05K1/0216 ,  H05K1/0234 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/167 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09318 ,  H05K2201/09327

Abstract: A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.

Abstract translation: 基板包括放置在彼此之间并且基本上彼此平行的电源平面和接地平面以及放置在电源平面和接地平面之间的至少一条信号线。 接地平面包括具有第一导电性的第一导电层。 功率平面包括具有第一导电性的第二导电层，并且功率平面或接地平面包括具有比第一导电率低的第二导电性的第三导电层。 第三导电层面对穿过电介质物质的至少一条信号线。

公开(公告)号：US20090155959A1

公开(公告)日：2009-06-18

申请号：US11958603

申请日：2007-12-18

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/50

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09736 ,  H05K2203/016 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a metal layer over the insulating polymer film layer. A solder mask can be formed over the metal layer. A conformal metal layer can then be formed over the solder mask. A notch can be formed in the insulation layer to enhance the connection between the insulating polymer film layer and the insulation layer. Additional semiconductor die can be electrically connected to the passive device. The substrate is removed by removing a first amount of the substrate using a back grind process, and then removing a second amount of the substrate using a wet dry, dry etch, or chemical-mechanical planarization process.

Abstract translation: 一种制造半导体器件的方法包括：在衬底的顶表面上设置绝缘层，在衬底的顶表面上形成无源器件，去除衬底，在绝缘层上沉积绝缘聚合物膜层 并且在绝缘聚合物膜层上沉积金属层。 可以在金属层上形成焊接掩模。 然后可以在焊接掩模上形成保形金属层。 可以在绝缘层中形成切口以增强绝缘聚合物膜层和绝缘层之间的连接。 另外的半导体管芯可以电连接到无源器件。 通过使用后研磨工艺去除第一量的基材，然后使用湿干，干蚀刻或化学机械平面化工艺除去第二量的基材来除去基材。

公开(公告)号：US20090073670A1

公开(公告)日：2009-03-19

申请号：US12076358

申请日：2008-03-17

Applicant: Jong-Kuk Hong ,  Jin-Yong An ,  Jae-Joon Lee

Inventor： Jong-Kuk Hong ,  Jin-Yong An ,  Jae-Joon Lee

IPC: H05K1/14 ,  H05K3/10 ,  H05K3/36 ,  H05K3/42

CPC classification number: H05K1/0271 ,  H05K1/09 ,  H05K3/205 ,  H05K3/207 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09781 ,  H05K2203/0152 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A multilayered printed circuit board and a fabricating method thereof are disclosed. A method that includes repeating processes of forming at least one circuit pattern, and at least one insulation layer that covers the circuit pattern, over a carrier and interconnecting circuit patterns on different layers with vias; stacking a metal stiffener over the insulation layer; repeating processes of forming at least one insulation layer and at least one circuit pattern over the stiffener and interconnecting circuit patterns on different layers with vias; and removing the carrier, can be used to reduce warpage in the board and improve workability.

Abstract translation: 公开了一种多层印刷电路板及其制造方法。 一种方法，其包括在载体上形成至少一个电路图案的重复处理和覆盖电路图案的至少一个绝缘层，并且在具有通孔的不同层上互连电路图案; 在绝缘层上堆叠金属加强件; 在加强件上形成至少一个绝缘层和至少一个电路图案的重复工艺，并且在具有通孔的不同层上互连电路图案; 并拆卸载体，可用于减少电路板翘曲，提高可加工性。

公开(公告)号：US20090038828A1

公开(公告)日：2009-02-12

申请号：US12108011

申请日：2008-04-23

Applicant: NING HOU ,  SHING-TZA LIOU

Inventor： NING HOU ,  SHING-TZA LIOU

IPC: H05K1/03 ,  B32B15/04

CPC classification number: H05K1/09 ,  B32B15/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/281 ,  B32B27/308 ,  B32B2457/08 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/022 ,  H05K3/384 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10T428/26 ,  Y10T428/31678

Abstract: The present invention relates to a flexible printed circuit board substrate and FPCB made from the flexible printed circuit board substrate. In one embodiment, a flexible printed circuit board substrate includes a dielectric layer, a rolled copper foil and an electroplated copper foil disposed on two opposite surfaces of the dielectric layer respectively. The contact fingers are made from electroplated copper foil, as a result, the contact fingers are stronger than that made from rolled copper foil. Furthermore, electroplated copper foils are cheaper than rolled copper foils.

Abstract translation: 本发明涉及由柔性印刷电路板基板制成的柔性印刷电路板基板和FPCB。 在一个实施例中，柔性印刷电路板基板包括分别设置在电介质层的两个相对表面上的电介质层，轧制铜箔和电镀铜箔。 接触指由电镀铜箔制成，其结果是，接触指比由轧制的铜箔制成的更牢固。 此外，电镀铜箔比轧制的铜箔便宜。

公开(公告)号：US20090008136A1

公开(公告)日：2009-01-08

申请号：US12213868

申请日：2008-06-25

Applicant: Nobuyuki Ikeguchi ,  Keungjin Sohn ,  Joon-Sik Shin

Inventor： Nobuyuki Ikeguchi ,  Keungjin Sohn ,  Joon-Sik Shin

IPC: H05K1/03 ,  H05K3/02

CPC classification number: H05K1/0271 ,  H01L23/5383 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K3/4641 ,  H05K3/4652 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/061 ,  Y10T29/49149 ,  Y10T29/49155 ,  H01L2224/05599

Abstract: A multilayered printed circuit board and a method of fabricating the printed circuit board are disclosed. The method of fabricating the multilayered printed circuit board can include: providing a core substrate, which has an outer circuit, and which has a thermal expansion coefficient of 10 to 20 ppm/° C. at −60 to 150° C.; stacking a stress-relieving insulation layer, which has a thermal expansion coefficient of −20 to 6 ppm/° C., on either side of the core substrate; and forming a metal layer on the insulation layer and forming at least one pad and electrically connecting the pad with the outer circuit. This method can provide high reliability, as the stress-relieving insulation layers can prevent bending and warpage, etc., in the board overall.

Abstract translation: 公开了一种多层印刷电路板和制造印刷电路板的方法。 制造多层印刷电路板的方法可以包括：提供具有外部电路的芯基板，并且在-60至150℃下具有10至20ppm /℃的热膨胀系数; 在芯基板的两侧堆叠热膨胀系数为-20〜6ppm /℃的应力消除绝缘层; 以及在所述绝缘层上形成金属层并且形成至少一个焊盘并将所述焊盘与所述外部电路电连接。 该方法可以提供高可靠性，因为应力消除绝缘层可以防止板的弯曲和翘曲等。

公开(公告)号：US20080171220A1

公开(公告)日：2008-07-17

申请号：US12036537

申请日：2008-02-25

Applicant: Takuya YAMAMOTO ,  Seiji Nagatani ,  Masahiko Nakano

Inventor： Takuya YAMAMOTO ,  Seiji Nagatani ,  Masahiko Nakano

IPC: B21C37/00

CPC classification number: B32B15/08 ,  B32B15/20 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/09 ,  H05K3/022 ,  H05K2201/0352 ,  H05K2201/0355 ,  Y10T428/12431 ,  Y10T428/12438 ,  Y10T428/31504 ,  Y10T428/31522

Abstract: To reduce warping of a copper clad laminate coated with copper foils of different thicknesses on both sides, and thereby to improve production efficiency of the printed-wiring boards, there is provided a copper clad laminate coated with copper foils of different thicknesses on both sides, wherein a first copper foil on one side of the laminate is not recrystallizable by hot pressing for production of said laminate and a second foil on the other side is recrystallizable by the hot pressing and thicker than the first foil.

Abstract translation: 为了减少在两面上涂覆有不同厚度的铜箔的覆铜层压板的翘曲，从而提高印刷电路板的生产效率，提供了一种涂覆有两侧不同厚度的铜箔的覆铜层压板， 其中层压体一侧的第一铜箔不能通过热压生成所述层压体而可再结晶，另一侧的第二箔可通过热压可再结晶并且比第一箔更厚。

公开(公告)号：US07368998B2

公开(公告)日：2008-05-06

申请号：US11608609

申请日：2006-12-08

Applicant: Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

Inventor： Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

IPC: H03F3/14 ,  H03H7/00

CPC classification number: H05K1/0265 ,  H01L2924/1423 ,  H03F3/195 ,  H03F2200/294 ,  H05K1/165 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0542

Abstract: An inductor element containing circuit board of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment) in one or more of the conductive layers, wherein at least part of the inductor conductor segment is made thicker than other conductors disposed within the circuit board. The at least part of the inductor conductor segment extends through an insulating layer disposed between the conductive layers, or is embedded in the insulating layer, wherein the part of the inductor conductor segment has a thickness one-half or more the thickness of the insulating layer. A power amplifier module of the present invention comprises the multi-layer circuit board, a semiconductor amplifier fabricated in the multi-layer circuit board, and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment.

Abstract translation: 本发明的电感器元件电路板包括多个导电层，以及在一个或多个导电层中具有电感器功能（电感器导体段）的导体，其中电感器导体段的至少一部分变厚 而不是设置在电路板内的其它导线。 电感器导体段的至少一部分延伸穿过设置在导电层之间的绝缘层，或者嵌入在绝缘层中，其中电感器导体段的一部分具有绝缘层的厚度的一半或更多的厚度 。 本发明的功率放大器模块包括多层电路板，在多层电路板中制造的半导体放大器和耦合到半导体放大器的输出的阻抗匹配电路。 阻抗匹配电路具有由电感器导体段形成的部分。

公开(公告)号：US07356917B2

公开(公告)日：2008-04-15

申请号：US11116320

申请日：2005-04-28

Applicant: Toshikazu Harada ,  Koji Kondo

Inventor： Toshikazu Harada ,  Koji Kondo

IPC: H05K3/30 ,  H05K1/03

CPC classification number: H05K1/0242 ,  H05K1/024 ,  H05K3/382 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2203/065 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T428/24917

Abstract: A multi-layer printed circuit board includes an insulation substrate; a surface conductive pattern disposed on a surface of the insulation substrate; and an inner conductive pattern embedded in the insulation substrate. The surface conductive pattern has a surface roughness on an insulation substrate side, the surface roughness of the surface conductive pattern being larger than that of the inner conductive pattern.

Abstract translation: 多层印刷电路板包括绝缘基板; 设置在所述绝缘基板的表面上的表面导电图案; 以及嵌入绝缘基板中的内导电图案。 表面导电图案在绝缘基板侧具有表面粗糙度，表面导电图案的表面粗糙度大于内部导电图案的表面粗糙度。

公开(公告)号：US07317245B1

公开(公告)日：2008-01-08

申请号：US11279002

申请日：2006-04-07

Applicant: Kyu Won Lee ,  Chan Yok Park ,  Sang Hyun Ryu

Inventor： Kyu Won Lee ,  Chan Yok Park ,  Sang Hyun Ryu

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L21/486 ,  H01L2924/0002 ,  H05K3/243 ,  H05K3/28 ,  H05K3/323 ,  H05K3/429 ,  H05K2201/0352 ,  H05K2203/054 ,  H05K2203/0542 ,  H05K2203/1394 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a method for manufacturing a semiconductor device substrate. A substrate having no bus line and lead-in line is efficiently manufactured. In a step needing an electroplating process, conductive film is temporarily attached to circuit patterns in order to electrically connect all circuit patterns. A plating is formed in desired regions of the circuit patterns with a predetermined thickness in an electroplating method. The conductive film is completely removed while the substrate is manufactured so that the circuit patterns are electrically independent of one another, and the resulting substrate has no bus line and lead-in line.

Abstract translation: 公开了半导体器件基板的制造方法。 没有总线和引入线的基板被有效地制造。 在需要电镀工艺的步骤中，导电膜临时连接到电路图案上，以便电连接所有电路图案。 在电镀方法中以预定的厚度在电路图案的期望区域中形成电镀。 在制造基板时，导电膜被完全去除，使得电路图案彼此电独立，并且所得到的基板没有总线和引入线。

公开(公告)号：US20070230078A1

公开(公告)日：2007-10-04

申请号：US11693316

申请日：2007-03-29

Applicant: Shin-ya Nakano ,  Yoh Takano ,  Tetsuro Sawai ,  Ryosuke Usui

Inventor： Shin-ya Nakano ,  Yoh Takano ,  Tetsuro Sawai ,  Ryosuke Usui

IPC: H02H5/04

CPC classification number: H01L23/142 ,  H01L23/3737 ,  H01L23/467 ,  H01L23/498 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0203 ,  H05K1/0265 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/10969 ,  H05K2203/0369 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A circuit device includes a metal substrate; and a plurality of circuit elements, mounted on the metal substrate, which electrically connects to the metal substrate. The metal substrate is made of a copper plate of high thermal conductivity. The metal substrate is demarcated into a plurality of sections by insulating films added with a filler for enhancing the thermal conductivity in resin. The circuit elements, which have respective independent operating potentials on a side of the metal substrate of the circuit elements, are respectively provided on separated copper plates.

Abstract translation: 电路装置包括金属基板; 以及多个电路元件，安装在与金属基板电连接的金属基板上。 金属基板由具有高导热性的铜板制成。 通过添加有填充剂的绝缘膜将金属基板划分为多个部分，以提高树脂中的导热性。 在电路元件的金属基板的一侧具有各自的独立工作电位的电路元件分别设置在分离的铜板上。