公开(公告)号：US08383461B2

公开(公告)日：2013-02-26

申请号：US12260231

申请日：2008-10-29

Applicant: Ki Yong Lee ,  Seung Kweon Ha

Inventor： Ki Yong Lee ,  Seung Kweon Ha

IPC: H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/4846 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H01L2224/05599

Abstract: A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Abstract translation: 一种制造半导体封装件的方法包括以下步骤：在载体衬底的上表面上形成第一电路图案。 凸起形成在限定在载体基板的上表面上的凹部中。 在载体基板的上表面上形成绝缘层以覆盖第一电路图案。 第二电路图案形成在绝缘层的上表面上，以便与第一电路图案电连接。 然后将载体衬底与绝缘层分离。

公开(公告)号：US20130000956A1

公开(公告)日：2013-01-03

申请号：US13616174

申请日：2012-09-14

Applicant: Yoshiyuki ISHIDA ,  Sadao Matsushima ,  Toshihide Fukuchi

Inventor： Yoshiyuki ISHIDA ,  Sadao Matsushima ,  Toshihide Fukuchi

IPC: H05K1/02

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/642 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/093 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09854 ,  H05K2201/10098 ,  H01L2924/00

Abstract: A high-frequency circuit board capable of easily forming a bias line whose resonance frequency is sufficiently separated from operating frequency is provided. On a high-frequency circuit board 100, by electrically connecting a bias line 11 to a high-frequency circuit 10 using blind via holes 106 and 107, it is possible to limit the route that has a possibility of producing resonance only to the bias line connecting the ends 106a and 107a of the blind via holes 106 and 107 to the bias line 11. By adjusting the route length from the end 106a to the end 107a, it is possible to prevent production of resonance in the vicinity of the operating frequency.

Abstract translation: 提供了能够容易地形成谐振频率与工作频率充分分离的偏置线的高频电路基板。 在高频电路板100上，通过使用盲通孔106和107将偏置线11与高频电路10进行电连接，可以限制仅具有产生谐振的可能性的路径到偏置线 将盲孔106和107的端部106a和107a连接到偏置线11.通过调整从端部106a到端部107a的路线长度，可以防止在工作频率附近产生谐振。

公开(公告)号：US08329311B2

公开(公告)日：2012-12-11

申请号：US11661047

申请日：2005-09-25

Applicant: François Marion ,  Cécile Davoine

Inventor： François Marion ,  Cécile Davoine

IPC: B23K35/02 ,  B32B15/01

CPC classification number: G03F7/0002 ,  B81C1/0046 ,  B82Y10/00 ,  B82Y40/00 ,  H05K3/04 ,  H05K3/062 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0108 ,  H05K2203/0113 ,  Y10T428/12222 ,  Y10T428/12354 ,  Y10T428/12382 ,  Y10T428/125 ,  Y10T428/12507 ,  Y10T428/12708 ,  Y10T428/12889 ,  Y10T428/24917

Abstract: The invention concerns a nanoprinted device comprising point shaped metallic patterns, in which each metallic pattern has a bilayer structure controlled in hardness and in chemical properties comprising a lower layer (30) constituting the base of the point and an upper layer (31) constituting the point itself.

Abstract translation: 本发明涉及包括点状金属图案的纳米印刷装置，其中每个金属图案具有硬度控制的双层结构和化学特性，包括构成该点的基底的下层（30）和构成该点的上层（31）的层 点自己。

公开(公告)号：US08322020B2

公开(公告)日：2012-12-04

申请号：US13227580

申请日：2011-09-08

Applicant: Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

Inventor： Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

IPC: H01F7/06

CPC classification number: H05K3/243 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2863 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/049 ,  H05K2203/0542 ,  H05K2203/0574 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49162 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49204

Abstract: A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads.

Abstract translation: 一种用于半导体测试探针卡的空间变压器及其制造方法。 该方法可以包括在具有限定第一间距间隔的多个第一接触测试焊盘的空间变压器基板上沉积第一金属层作为接地平面，在接地平面上沉积第一介电层，形成多个第二测试触点， 与所述第一间距间隔不同的第二间距间隔，以及在所述第一介电层上形成多个再分配引线，以将所述第一接触测试焊盘电耦合到所述第二接触测试焊盘。 在一些实施例中，再分配引线可以直接构建在空间变换器基板上。 该方法可以在一个实施例中用于重新制造现有空间变压器以产生具有小于原始测试焊盘的间距间距的细间距测试焊盘。

公开(公告)号：US08309856B2

公开(公告)日：2012-11-13

申请号：US12264386

申请日：2008-11-04

Applicant: Nobuhisa Kuroda ,  Naoki Kubota

Inventor： Nobuhisa Kuroda ,  Naoki Kubota

IPC: H05K1/09

CPC classification number: H05K3/244 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3463 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/043 ,  H05K2203/0594 ,  Y10T428/24917

Abstract: A circuit board and method of manufacturing a circuit board. The circuit board includes a substrate, a conductor layer formed on the substrate, and an insulation layer formed on the substrate and the conductor layer, the insulating layer having an opening with an undercut therein, the opening reaching the conductor layer. A metal layer is formed in the opening of the insulation layer and connected to the conductor layer, a solder layer formed in the opening of the insulation layer and outside of the opening; and an alloy layer formed in a boundary region between the metal layer and the solder layer in the opening. The alloy layer includes a metal of the metal layer and a composition of the solder layer, the alloy layer being more fragile than the metal layer and being formed in a position misaligned from an edge of the undercut of the opening formed on the insulation layer.

Abstract translation: 一种电路板及其制造方法。 电路板包括基板，形成在基板上的导体层，以及形成在基板和导体层上的绝缘层，绝缘层具有开口，底部具有底切，开口到达导体层。 在绝缘层的开口部形成金属层，与导体层连接，在绝缘层的开口部和开口部的外侧形成有焊料层， 以及形成在开口中的金属层和焊料层之间的边界区域中的合金层。 合金层包括金属层的金属和焊料层的组成，合金层比金属层更脆弱，并且形成在与形成在绝缘层上的开口的底切的边缘不对准的位置。

公开(公告)号：US08302298B2

公开(公告)日：2012-11-06

申请号：US12835085

申请日：2010-07-13

Applicant: Chen-Yueh Kung ,  Wei-Cheng Chen

Inventor： Chen-Yueh Kung ,  Wei-Cheng Chen

IPC: H01K3/10

CPC classification number: H05K3/4007 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for fabricating a circuit substrate is provided. A patterned conductive layer having an inner pad is provided on a base layer, a dielectric layer is disposed on the base layer and covers the patterned conductive layer, and a covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second opening is formed. Finally, the patterned mask, surplus layer and covering layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 具有内垫的图案化导电层设置在基底层上，电介质层设置在基底层上并覆盖图案化的导电层，并且覆盖层设置在电介质层上。 通过干蚀刻去除覆盖层的一部分以形成第一开口。 去除由第一开口暴露的电介质层的一部分，以形成暴露一部分内垫的电介质开口。 在覆盖层上形成具有第二开口以露出内部衬垫的一部分的图案化掩模。 形成包括填充电介质开口的导电块，填充第一开口的外垫和填充第二开口的剩余层的导电结构。 最后，去除图案化掩模，剩余层和覆盖层。

公开(公告)号：US20120267155A1

公开(公告)日：2012-10-25

申请号：US13543547

申请日：2012-07-06

Applicant: Chen-Yueh Kung

Inventor： Chen-Yueh Kung

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/0361 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1152 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit substrate includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block.

Abstract translation: 电路基板包括基底层，图案化导电层，电介质层，外部焊盘和导电块。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 外垫设置在电介质层上。 导电层通过电介质层并连接在外焊盘和内焊盘之间，其中外焊盘和导电块形成为整体单元，外焊盘的外径基本上等于外焊盘 的导电块。

公开(公告)号：US08279618B2

公开(公告)日：2012-10-02

申请号：US12717170

申请日：2010-03-04

Applicant: Yutaka Fukuda

Inventor： Yutaka Fukuda

IPC: H05K7/10 ,  H05K7/00 ,  H05K1/16

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11003 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/245 ,  H05K3/3436 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2203/0191 ,  H05K2203/0278 ,  H05K2203/308 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A circuit substrate includes protruding terminals and has a structure that ensures an excellent connection with an electronic component, such as an IC. The circuit substrate on which an IC is to be mounted includes terminals that are to be electrically connected to solder bumps located on the IC. The terminals protrude from the mounting surface of a substrate body on which the IC is to be mounted. The sectional area of the top surface of each of the terminals is about 1.2 times the sectional area of each of the terminals on the mounting surface.

Abstract translation: 电路基板包括突出端子，并且具有确保与诸如IC的电子部件的良好连接的结构。 要安装IC的电路基板包括要与位于IC上的焊料凸块电连接的端子。 端子从要安装IC的基板主体的安装表面突出。 每个端子的顶表面的截面面积是安装表面上每个端子的截面积的约1.2倍。

公开(公告)号：US08237270B2

公开(公告)日：2012-08-07

申请号：US13034083

申请日：2011-02-24

Applicant: Kazuhiro Kobayashi ,  Junichi Nakamura ,  Kentaro Kaneko

Inventor： Kazuhiro Kobayashi ,  Junichi Nakamura ,  Kentaro Kaneko

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2201/2072 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract translation: 半导体器件100具有半导体芯片110被倒装安装在布线板120上的结构。布线板120具有多层结构，其中布置有多个布线层和多​​个绝缘层，并且具有 提供第一层122，第二层124，第三层126和第四层128的绝缘层的结构。 第一层122具有第一绝缘层121和第二绝缘层123.在第一电极焊盘130的一个表面侧的外周沿径向（周向）突出的突出部132形成在 在第一绝缘层121和第二绝缘层123之间的边界表面上的整个外围。

公开(公告)号：US20120175265A1

公开(公告)日：2012-07-12

申请号：US13426461

申请日：2012-03-21

Applicant: Sao-Hsia Tang ,  Ying-Tung Wang

Inventor： Sao-Hsia Tang ,  Ying-Tung Wang

IPC: H05K3/00 ,  C25D5/02

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13017 ,  H01L2224/13018 ,  H05K3/243 ,  H05K3/3473 ,  H05K3/3484 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/054 ,  H05K2203/0577 ,  H05K2203/0594 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01024

Abstract: A circuit board surface structure and a fabrication method thereof are proposed. The circuit board surface structure includes: a circuit board having a plurality of electrically connecting pads formed on at least one surface thereof; a first and a second insulating protective layers formed on the surface of the circuit board in sequence; first and a second openings respectively formed in the first and second insulating protective layers to expose the electrically connecting pads on the surface of the circuit board, wherein the first and second openings have narrow top and wide bottom and the diameter of the first openings is bigger than that of the second openings; and conductive elements formed in the first and second openings on surfaces of the electrically connecting pads. The present structure facilitates to strengthen the bonding between the conductive elements and the corresponding electrically connecting pads.

Abstract translation: 提出了一种电路板表面结构及其制造方法。 电路板表面结构包括：具有形成在其至少一个表面上的多个电连接焊盘的电路板; 依次形成在电路板的表面上的第一和第二绝缘保护层; 分别形成在第一和第二绝缘保护层中的第一和第二开口以暴露电路板表面上的电连接焊盘，其中第一和第二开口具有窄的顶部和宽底部，并且第一开口的直径较大 比第二个开口; 以及形成在电连接焊盘的表面上的第一和第二开口中的导电元件。 本结构有助于加强导电元件与相应的电连接焊盘之间的接合。