公开(公告)号：US20140085890A1

公开(公告)日：2014-03-27

申请号：US13720684

申请日：2012-12-19

Applicant: TOSHIBA LIGHTING & TECHNOLOGY CORPORATION

Inventor： Kazuya KONDO ,  Yuichiro TAKAHARA

IPC: F21V21/00

CPC classification number: F21V21/00 ,  F21K9/20 ,  F21S8/026 ,  F21V23/06 ,  F21V29/507 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L2924/0002 ,  H05K1/11 ,  H05K2201/09227 ,  H05K2201/10106 ,  Y10T29/49002 ,  H01L2924/00

Abstract: According to one embodiment, a light-emitting device includes a substrate, a first light-emitting element group, a second light-emitting element group, and a terminal group. The first light-emitting element group includes plural first light-emitting elements mounted on the substrate. The second light-emitting element group is mounted on the substrate alongside the first light-emitting element group and includes plural second light-emitting elements. The terminal group includes plural terminals electrically connected to the first light-emitting element group and the second light-emitting element group, and is arranged on a side of the first light-emitting element group opposite to a side thereof facing the second light-emitting element group in a first direction in which the first light-emitting element group and the second light-emitting element group on the substrate are arranged side by side.

Abstract translation: 根据一个实施例，发光器件包括衬底，第一发光元件组，第二发光元件组和端子组。 第一发光元件组包括安装在基板上的多个第一发光元件。 第二发光元件组与第一发光元件组一起安装在基板上，并且包括多个第二发光元件。 端子组包括电连接到第一发光元件组和第二发光元件组的多个端子，并且布置在第一发光元件组的与面向第二发光元件组的一侧相反的一侧 元件组在基板上的第一发光元件组和第二发光元件组并列配置的第一方向。

公开(公告)号：US20130329390A1

公开(公告)日：2013-12-12

申请号：US13785137

申请日：2013-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Onpil SHIN ,  Minho SEO

IPC: H05K1/02

CPC classification number: H05K1/025 ,  G11C5/02 ,  G11C7/10 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2924/00

Abstract: A semiconductor device includes a package board having a front side and a back side opposite to each other. A first memory device has data pins and is mounted on the front side of the package board, and a second memory device has data pins and is mounted on the back side of the package board. The data pins of the first and second memory devices have a same arrangement. A controller provides data signals to the first and second memory devices, with the same data signal provided from the controller to one data pin of the first memory device and one data pin of the second memory device.

Abstract translation: 半导体器件包括具有彼此相对的前侧和后侧的封装板。 第一存储器件具有数据引脚并且被安装在封装板的前侧，并且第二存储器件具有数据引脚并安装在封装板的背面上。 第一和第二存储器件的数据引脚具有相同的布置。 控制器向第一和第二存储器件提供数据信号，其中从控制器提供的数据信号与第一存储器件的一个数据引脚和第二存储器件的一个数据引脚相同。

公开(公告)号：US20130286644A1

公开(公告)日：2013-10-31

申请号：US13563738

申请日：2012-08-01

Applicant: CHIH-CHEN LAI

Inventor： CHIH-CHEN LAI

IPC: F21V21/00

CPC classification number: H05K1/167 ,  F21S4/20 ,  F21Y2103/10 ,  F21Y2115/10 ,  H05K1/0296 ,  H05K1/111 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09663 ,  H05K2201/10106 ,  Y02P70/611

Abstract: An LED light bar includes LED chips and a printed circuit board. A number of welding pads are disposed on the printed circuit board, and correspondingly connected to anodes and cathodes of the LED chips respectively. The welding pads connected to the anodes of the LED chips are connected by wire lines for connecting an anode of an electrical power source. The welding pads connected to the cathodes of the LED chips are connected by the wire lines for connecting a cathode of the electrical power source. The resistance of the wire lines connected to the LED chips increases from one near the electrical power source to the one far from the electrical power source. The resistance of the welding pads connected to the LED chips decreases from one near the electrical power source to the one far from the electrical power source.

Abstract translation: LED灯条包括LED芯片和印刷电路板。 多个焊盘设置在印刷电路板上，分别相应地连接到LED芯片的阳极和阴极。 连接到LED芯片的阳极的焊盘通过用于连接电源的阳极的线路连接。 连接到LED芯片的阴极的焊盘通过用于连接电源的阴极的电线连接。 连接到LED芯片的电线的电阻从电源附近的电阻增加到远离电源的电阻。 连接到LED芯片的焊盘的电阻从电源附近的电阻减小到远离电源的电阻。

公开(公告)号：US08493765B2

公开(公告)日：2013-07-23

申请号：US13365358

申请日：2012-02-03

Applicant: Takayuki Yoshida ,  Mitsumi Itou ,  Shinya Tokunaga

Inventor： Takayuki Yoshida ,  Mitsumi Itou ,  Shinya Tokunaga

IPC: G11C5/06

CPC classification number: H05K1/0243 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K1/141 ,  H05K2201/09227 ,  H05K2201/10159 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: All interface pins for transmitting and receiving a signal having a predetermined function of a semiconductor integrated circuit element are formed on an outer periphery of the semiconductor integrated circuit element along one side of the semiconductor integrated circuit element. The one side of the semiconductor integrated circuit element is adjacent to two of sides of a BGA substrate, the two sides being not parallel to the one side. Of balls provided on the BGA substrate, balls electrically connected to the interface pins for transmitting and receiving a signal having a predetermined function are provided between the one side of the semiconductor integrated circuit element and the two sides of the BGA substrate.

Abstract translation: 用于发送和接收具有半导体集成电路元件的预定功能的信号的所有接口引脚沿半导体集成电路元件的一侧形成在半导体集成电路元件的外周上。 半导体集成电路元件的一侧与BGA基板的两侧相邻，两侧不平行于一侧。 设置在BGA基板上的球体，在半导体集成电路元件的一侧和BGA基板的两侧之间设置电连接到用于发送和接收具有预定功能的信号的接口引脚的滚珠。

公开(公告)号：US08383951B2

公开(公告)日：2013-02-26

申请号：US12604465

申请日：2009-10-23

Applicant: Danny L. C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan DeGeest

Inventor： Danny L. C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan DeGeest

IPC: H05K1/11

CPC classification number: H05K1/114 ,  H05K1/0219 ,  H05K1/0237 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10189 ,  H05K2201/10734

Abstract: Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.

Abstract translation: 公开了用于在诸如印刷电路板的基板上定义匹配阻抗覆盖区的方法，例如适于接收具有端子引线布置的电气部件。 这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。 通孔布置可以不同于衬垫布置。 通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。 可以改变通孔布置以在板的层上实现期望的布线密度。 增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。 接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。 因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。 也可以改变通孔装置以限制相邻信号导体之间的串扰。 因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

公开(公告)号：US20130033669A1

公开(公告)日：2013-02-07

申请号：US13375479

申请日：2011-08-26

Applicant: Liangchan Liao ,  Poshen Lin ,  Yu Wu

Inventor： Liangchan Liao ,  Poshen Lin ,  Yu Wu

IPC: G02F1/1345 ,  H05K7/06

CPC classification number: G02F1/13452 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2224/97 ,  H01L2924/15162 ,  H01L2924/15788 ,  H05K2201/09227 ,  H05K2201/10681 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: The present invention discloses a tape substrate for chip on film structure of a liquid crystal panel. The tape substrate is provided with plural package units of chip on film structures arranged along its longitudinal direction, and the package unit has a driver chip, input leads and output leads. The longitudinal direction of the driver chip is parallel to the longitudinal direction of the tape substrate, and the input leads and the output leads are located at the two opposite sides of the driver chip. Each package unit is set up with a short side and a long side, and the input leads are formed at the short side, while the output leads are formed at the long side. In the package units adjacent to each other, the short side of one package unit joins the long side of a next package unit. This invention further discloses a liquid crystal panel having the tape substrate.

Abstract translation: 本发明公开了一种液晶面板的薄膜结构用芯片基片。 带状基板设置有沿着其纵向方向布置的多个封装在膜结构上的封装单元，并且封装单元具有驱动器芯片，输入引线和输出引线。 驱动器芯片的纵向平行于带基板的纵向方向，并且输入引线和输出引线位于驱动器芯片的两个相对侧。 每个封装单元设置有短边和长边，并且输入引线形成在短边，而输出引线形成在长边。 在彼此相邻的包装单元中，一个包装单元的短边连接下一个包装单元的长边。 本发明还公开了一种具有带基片的液晶面板。

公开(公告)号：US08369099B2

公开(公告)日：2013-02-05

申请号：US12656451

申请日：2010-01-29

Applicant: Do Hyung Kim ,  Jung-Mo Yang ,  Hyun Jung Yoo ,  Dong-Yoon Seo ,  In-Young Park

Inventor： Do Hyung Kim ,  Jung-Mo Yang ,  Hyun Jung Yoo ,  Dong-Yoon Seo ,  In-Young Park

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/10159 ,  Y02P70/611

Abstract: Disclosed is an electronic device module including a module substrate having first and second electronic device pair portions. The first electronic device pair portion may include a first and a second contact pad area and a first via area between the first and second contact pad areas. The first electronic device pair portion may also include a first layer and a second layer. The first layer may include a plurality of first lines connecting a plurality of contact pads in the first contact pad area on one side of the module substrate to a plurality of vias. The second layer may include a plurality of second lines connecting a plurality of contact pads in the second contact pad area to a plurality of vias in the via area. The second layer may also include a plurality of third lines connecting the first and second electronic device pair portions.

Abstract translation: 公开了一种电子设备模块，包括具有第一和第二电子设备对部分的模块基板。 第一电子器件对部分可以包括第一和第二接触焊盘区域和第一和第二接触焊盘区域之间的第一通孔区域。 第一电子设备对部分还可以包括第一层和第二层。 第一层可以包括将模块衬底的一侧上的第一接触焊盘区域中的多个接触焊盘连接到多个通孔的多条第一线。 第二层可以包括将第二接触焊盘区域中的多个接触焊盘连接到通孔区域中的多个通孔的多条第二线路。 第二层还可以包括连接第一和第二电子设备对部分的多条第三线。

公开(公告)号：US08364926B2

公开(公告)日：2013-01-29

申请号：US13408950

申请日：2012-02-29

Applicant: Craig E. Hampel ,  Frederick A. Ware

Inventor： Craig E. Hampel ,  Frederick A. Ware

IPC: G06F12/00

CPC classification number: G06F13/1642 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/4243 ,  G06F2212/656 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1075 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract translation: 具有减小的访问粒度的存储器模块。 存储器模块包括其上具有信号线的衬底，其形成控制路径和第一和第二数据路径，并且还包括共同耦合到控制路径并分别耦合到第一和第二数据路径的第一和第二存储器件。 第一和第二存储器件包括控制电路，用于响应于第一和第二存储器访问命令，经由控制路径接收相应的第一和第二存储器访问命令并且执行第一和第二数据路径上的并发数据传输。

公开(公告)号：US08344266B2

公开(公告)日：2013-01-01

申请号：US11837322

申请日：2007-08-10

Applicant: Steven C. Bird ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

Inventor： Steven C. Bird ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

Abstract translation: 提供了用于优化专用集成电路（ASIC）和对应于高密度互连（HDI）印刷电路板（PCB）布局）的其他IC引脚分配的技术。 应用本文描述的技术，可以系统地和策略性地规划引脚分配，例如，为了减少PCB层数量和相关成本，增加信号完整性和速度，减少由ASIC及其支持电路使用的表面积， 与安装在多层PCB上的ASIC的传统设计相比，减少了平面穿孔，并减少了串扰。

公开(公告)号：US08284564B2

公开(公告)日：2012-10-09

申请号：US12697737

申请日：2010-02-01

Applicant: Satoshi Mizuno

Inventor： Satoshi Mizuno

IPC: H01R9/00

CPC classification number: H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A circuit board includes balls as electrodes in a grid, a power supply wiring pattern area connected to power supply terminals of an integrated circuit mounted thereon, and a feeding pattern area connected to a feeding point; the balls include first and second power supply ball groups connected respectively to power supply terminal arrays, at a predetermined interval, of the integrated circuit, and the power supply wiring pattern area includes first and second power supply connection patterns connected respectively to the first and second ball groups, and at least one connection pattern connecting the first and second power supply connection patterns noncontact to the balls, and has first and second connection portions connected respectively to the feeding pattern area and one electrode of a first bypass capacitor, and the second power supply connection pattern has a third connection portion connected to one electrode of a second bypass capacitor.

Abstract translation: 电路板包括作为电网中的电极的球，连接到安装在其上的集成电路的电源端子的电源布线图形区域和连接到馈电点的馈电图案区域; 所述球包括以集成电路的预定间隔分别连接到电源端子阵列的第一和第二电源球组，并且电源布线图案区域包括分别连接到第一和第二电源连接图案的第一和第二电源连接图案 球组，以及将第一和第二电源连接图案连接到球的至少一个连接图案，并且具有分别连接到馈送图案区域和第一旁路电容器的一个电极的第一和第二连接部分，并且第二电力 供电连接图案具有连接到第二旁路电容器的一个电极的第三连接部分。