公开(公告)号：US09086874B2

公开(公告)日：2015-07-21

申请号：US13491353

申请日：2012-06-07

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: H05K7/00 ,  G06F1/32 ,  H05K1/02 ,  H01L23/32 ,  H05K1/14 ,  H05K1/18

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, and peripheral circuit modules residing on the interposer substrate, wherein each peripheral circuit module has an electrical path having a path length to the main processor less than one-quarter of a wavelength of signals that will travel the electrical path.

Abstract translation: 计算装置具有电路基板，具有插座，插入插座的主处理器，插入在插座和主处理器之间的插入器基板，电连接的电路基板，插座和插入器基板，以及外围电路模块 在所述插入器基板上，其中每个外围电路模块具有电路径，所述电路径具有到主处理器的路径长度小于将传播电路径的信号的波长的四分之一。

公开(公告)号：US20140326495A1

公开(公告)日：2014-11-06

申请号：US14240960

申请日：2012-08-27

Applicant: Jose Ricardo Paniagua

Inventor： Jose Ricardo Paniagua

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/10 ,  H05K3/00

CPC classification number: H05K1/116 ,  G06F17/5081 ,  G06F2217/82 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/0784 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/09718 ,  H05K2201/09727 ,  H05K2203/0207 ,  H05K2203/0242 ,  Y10T29/49165

Abstract: A printed circuit board for carrying high frequency signals. Conducting structures of the printed circuit board are shaped within breakout regions to limit impedance discontinuities in the signal paths between vias and conductive traces within the printed circuit board. Values of parameters of traces or anti-pads, for example, may be adjusted to provide a desired impedance. The specific values selected as part of designing a printed circuit board may match the impedance of the breakout region to that of the via. The parameters for which values are selected may include the trace width, thickness, spacing, length over an anti-pad or angle of exit from the breakout region.

Abstract translation: 用于承载高频信号的印刷电路板。 印刷电路板的导电结构在突出区域内成形，以限制印刷电路板内的通孔和导电迹线之间的信号路径中的阻抗不连续性。 痕迹或抗焊盘参数的值可以被调整以提供所需的阻抗。 选择作为设计印刷电路板的一部分的具体值可以将突破区域的阻抗与通孔的阻抗匹配。 选择值的参数可以包括迹线宽度，厚度，间隔，防焊盘上的长度或从断裂区域的出口角度。

公开(公告)号：US20120262863A1

公开(公告)日：2012-10-18

申请号：US13491378

申请日：2012-06-07

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: G06F1/16

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.

Abstract translation: 计算设备具有具有至少一层电互连层的母板电路基板和布置成接收用于计算设备的主处理器的插座，插座电耦合到电互连层的至少一部分，其中电路基板 没有内存互连。

公开(公告)号：US20120262862A1

公开(公告)日：2012-10-18

申请号：US13491353

申请日：2012-06-07

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: G06F1/16

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, and peripheral circuit modules residing on the interposer substrate, wherein each peripheral circuit module has an electrical path having a path length to the main processor less than one-quarter of a wavelength of signals that will travel the electrical path.

Abstract translation: 计算装置具有电路基板，具有插座，插入插座的主处理器，插入在插座和主处理器之间的插入器基板，电连接的电路基板，插座和插入器基板，以及外围电路模块 在所述插入器基板上，其中每个外围电路模块具有电路径，所述电路径具有到主处理器的路径长度小于将传播电路径的信号的波长的四分之一。

公开(公告)号：US12069805B2

公开(公告)日：2024-08-20

申请号：US17482943

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Chi V. Pham ,  Xiaofang Mu

IPC: H05K1/00 ,  H01P3/08 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/116 ,  H01P3/08 ,  H05K1/0243 ,  H05K2201/095

Abstract: Devices are disclosed that include a wideband millimeter wave (mmW) via transition design for multilayer printed circuit boards (MLBs). In various instances embodiments, a via is dimensioned to provide impedance matching to stripline tracing connected at the end of the via. Impedance matching in the via may eliminate the need for an impedance matching section on the stripline tracing. In some instances, the dimensions of the via pad diameter and the via keepout diameter are selected to tune a via transition structure to selected frequencies and/or frequency bandwidths.

公开(公告)号：US12046966B2

公开(公告)日：2024-07-23

申请号：US17740690

申请日：2022-05-10

Applicant: INFINITUM ELECTRIC, INC.

Inventor： Rich Lee ,  Randal A. Lee ,  Paulo Guedes-Pinto

IPC: H02K9/22 ,  H01F17/00 ,  H01F27/22 ,  H01F27/28 ,  H02K1/12 ,  H02K1/18 ,  H02K3/26 ,  H02K11/26 ,  H02K11/30 ,  H02K21/24 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16

CPC classification number: H02K3/26 ,  H01F17/0013 ,  H01F27/22 ,  H01F27/2804 ,  H02K1/12 ,  H02K1/182 ,  H02K9/22 ,  H02K11/26 ,  H02K11/30 ,  H02K21/24 ,  H05K1/0201 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/165 ,  H01F2017/002 ,  H01F2017/0053 ,  H01F2027/2809 ,  H02K2203/03 ,  H02K2211/03 ,  H05K2201/093 ,  H05K2201/095 ,  H05K2201/10416

Abstract: An axial field rotary energy device has a PCB stator panel assembly between rotors with an axis of rotation. Each rotor has a magnet. The PCB stator panel assembly includes PCB panels. Each PCB panel can have layers, and each layer can have conductive coils. The PCB stator panel assembly can have a thermally conductive layer that extends from an inner diameter portion to an outer diameter portion thereof.

公开(公告)号：US12028968B2

公开(公告)日：2024-07-02

申请号：US17312001

申请日：2018-12-19

Applicant: Sony Group Corporation

Inventor： Takahiro Shinojima

IPC: H03H7/38 ,  H01P1/04 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/025 ,  H01P1/04 ,  H03H7/38 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/11 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/095

Abstract: Provided is an example of a technology capable of accurately controlling impedance.
Provided is a substrate including a first through hole that penetrates a substrate from a first face to a second face of the substrate, and is electrically connected to a transmission line through which a signal is transmitted, a second through hole that is provided adjacent to the first through hole in plan view of the substrate, penetrates the substrate from the first face to the second face, and is electrically connected to a ground, and an adjustment unit that adjusts a distance between the first through hole and the second through hole in plan view of the substrate to adjust an impedance of a connection end of the first through hole with the transmission line.

公开(公告)号：US20240147612A1

公开(公告)日：2024-05-02

申请号：US18278253

申请日：2022-07-08

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Kenji TAKAHASHI ,  Shoichiro SAKAI

IPC: H05K1/02

CPC classification number: H05K1/0298 ,  H05K2201/0352 ,  H05K2201/095

Abstract: A printed wiring board includes a base and a conductor layer. A through hole reaching the second surface from the first surface is formed in the base. A first opening of the through hole is formed in the first surface of the base. A second opening of the through hole is formed in the second surface of the base. A conductor layer is disposed inside the through hole. The base includes a first protrusion. The first protrusion protrudes from an edge portion of the first opening. The first opening has a first opening width in a first cross section passing through the first protrusion and a center of the first opening and taken along a thickness direction of the base. The second opening has a second opening width in the first cross section. The first opening width is smaller than the second opening width.

公开(公告)号：US20240090134A1

公开(公告)日：2024-03-14

申请号：US18515892

申请日：2023-11-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito OTSUBO ,  Hirofumi OIE

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H05K2201/0212 ,  H05K2201/0707 ,  H05K2201/09472 ,  H05K2201/095 ,  H05K2201/1006 ,  H05K2201/10098 ,  H05K2201/10287

Abstract: An electronic circuit module includes: a substrate; a first electronic component mounted on one main surface of the substrate; a substrate electrode provided on the one main surface; a second electronic component supported on a support surface opposite to a surface facing the one main surface of the first electronic component; a conductor provided on the support surface of the first electronic component; a wire connected to the conductor and the substrate electrode; and a component electrode provided on a surface of the second electronic component and electrically connected to the conductor.

公开(公告)号：US20240063110A1

公开(公告)日：2024-02-22

申请号：US18492816

申请日：2023-10-24

Applicant: CHUN-MING LIN

Inventor： CHUN-MING LIN

IPC: H01L23/498 ,  C25D7/12 ,  H01L21/48 ,  C25D3/38 ,  H05K1/11 ,  H05K1/09

CPC classification number: H01L23/49866 ,  H01L23/49822 ,  C25D7/12 ,  H01L21/4857 ,  C25D3/38 ,  H01L23/49827 ,  H05K1/112 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/0364 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K1/18

Abstract: The present disclosure provides a method for forming a multilayer wiring structure, which includes: forming a patterned copper-phosphorous alloy layer over a carrier by performing a plating operation, and forming a dielectric layer over the patterned copper-phosphorous alloy layer. The forming the patterned copper-phosphorous alloy layer includes providing a plating solution having a copper source and a phosphorous source.