公开(公告)号：US20130017321A1

公开(公告)日：2013-01-17

申请号：US13251998

申请日：2011-10-03

Applicant: Young Jae Kim ,  Ha Yoon Song ,  Ho Joon Park

Inventor： Young Jae Kim ,  Ha Yoon Song ,  Ho Joon Park

IPC: B05D5/12 ,  B05D3/00

CPC classification number: G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H05K3/048 ,  H05K3/1216 ,  H05K3/1258 ,  H05K2201/09681

Abstract: A method for forming a metal mesh electrode of a touch panel of the present invention can solve a depletion problem of resources used for a transparent conductive layer by forming an electrode using a metal thin film on which fine patterns are formed, instead of using ITO and form a metal mesh electrode having a fine line width while controlling a height by using a screen printing method using a photoresist layer and a printing mask together.

Abstract translation: 本发明的触摸面板的金属网状电极的形成方法可以通过使用形成精细图案的金属薄膜来形成电极，而不是使用ITO而形成用于透明导电层的资源的耗尽问题 通过使用使用光致抗蚀剂层和印刷掩模的丝网印刷法同时控制高度来形成具有细线宽度的金属网状电极。

公开(公告)号：US08339803B2

公开(公告)日：2012-12-25

申请号：US12630993

申请日：2009-12-04

Applicant: Wiren Dale Becker ,  Jinwoo Choi ,  Tingdong Zhou

Inventor： Wiren Dale Becker ,  Jinwoo Choi ,  Tingdong Zhou

IPC: H05K7/00

CPC classification number: H01L21/76838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K3/4629 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.

Abstract translation: 多层陶瓷封装包括：具有识别的芯片/设备区域/需要供电电源的位置的信号层; 以及设置在信号层的正上方或下方（相邻）相对侧的电压功率（Vdd）层和接地（Gnd）层，并且提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。 混合网格方案包括以下不同的网格配置：在识别的芯片/设备区域之上或之下的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 并且在所有其它区域中具有更宽的网格间距，并且Vdd迹线对准以在其他区域中与信号线平行并相邻地延伸。 在与信号线平行且相邻的网格区域内提供更宽的轨迹。

公开(公告)号：US08288657B2

公开(公告)日：2012-10-16

申请号：US12577259

申请日：2009-10-12

Applicant: Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

Inventor： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

IPC: H05K1/00

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

Abstract: An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.

Abstract translation: 一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线 第一条信号线。 多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

公开(公告)号：US20120235141A1

公开(公告)日：2012-09-20

申请号：US13418619

申请日：2012-03-13

Applicant: Hayato MASUBUCHI ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

Inventor： Hayato MASUBUCHI ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

IPC: H01L23/58 ,  H01L23/48

CPC classification number: H01L25/18 ,  G11C5/02 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/115 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/613 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

Abstract translation: 根据一个实施例，半导体存储器系统包括衬底，多个元件和粘合剂部分。 基板具有其中形成布线图案并且在平面图中具有大致矩形形状的多层结构。 元件沿着衬底的表面层侧的长边方向设置和布置。 粘合剂部分填充在元件之间的间隙中，并且在元件和基板之间的间隙中填充元件的表面。

公开(公告)号：US20120234591A1

公开(公告)日：2012-09-20

申请号：US13437254

申请日：2012-04-02

Applicant: Han KIM ,  Mi-Ja Han ,  Hyo-Jic Jung

Inventor： Han KIM ,  Mi-Ja Han ,  Hyo-Jic Jung

IPC: H05K1/11

CPC classification number: H01P1/2005 ,  H01L2224/16 ,  H01P1/203 ,  H05K1/0236 ,  H05K1/0237 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/09681

Abstract: An electromagnetic bandgap structure including: at least three conductive plates; a first stitching via, configured to electrically connect any one of the conductive plates to another conductive plate; and a second stitching via, configured to electrically connect the one conductive plate to yet another conductive plate, wherein the first stitching via electrically connects the one conductive plate to another conductive plate by allowing a part of the first stitching via to be connected through a planar surface above or below the one conductive plate, and the second stitching via electrically connects the one conductive plate to yet another conductive plate by allowing a part of the second stitching via to be connected through a planar surface that is different from the planar surface through which the part of the first stitching via is connected, the two planar surfaces being placed in a same direction based on the conductive plates.

Abstract translation: 一种电磁带隙结构，包括：至少三个导电板; 第一缝合通孔，被配置为将任一导电板电连接到另一个导电板; 以及第二缝合通孔，其被配置为将所述一个导电板电连接到另一个导电板，其中所述第一缝合通孔将所述第一缝合通孔的一部分通过平面 表面在一个导电板的上方或下方，并且第二缝合通孔通过允许第二缝合通孔的一部分通过不同于平面的平面表面连接一个导电板到另一个导电板，通过该平面 第一缝合通孔的部分被连接，两个平面被放置在相同的方向上，基于导电板。

公开(公告)号：US08228681B2

公开(公告)日：2012-07-24

申请号：US12607571

申请日：2009-10-28

Applicant: Gil Ju Jin ,  Jung Lim Park ,  Jae Yk Kim

Inventor： Gil Ju Jin ,  Jung Lim Park ,  Jae Yk Kim

IPC: H05K7/00

CPC classification number: A61B8/4494 ,  A61B8/00 ,  A61B8/4461 ,  A61B8/4483 ,  B06B1/0622 ,  H05K1/189 ,  H05K3/305 ,  H05K2201/055 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2201/10083 ,  H05K2201/10462 ,  Y02P70/613

Abstract: Disclosed herein are a printed circuit board (PCB) and a probe including the same. The probe includes a transducer, a PCB having a pattern part contacting the transducer via face-to-face contact, and a bonding member bonding the transducer to the pattern part of the PCB. The bonding part of the PCB is provided with the pattern part to increase a bonding area of the bonding part and to allow the bonding member to contact not only a metal layer of the bonding part but also an electrical insulation part thereof, thereby improving a bonding force between the transducer and the PCB. As a result, the transducer can be reliably bonded to the PCB, so that performance of the transducer can be prevented from being deteriorated due to defective connection between the PCB and the transducer.

Abstract translation: 这里公开了印刷电路板（PCB）和包括该电路板的探针。 探头包括换能器，具有经由面对面接触与换能器接触的图案部分的PCB以及将换能器接合到PCB的图案部分的接合构件。 PCB的接合部分设置有图案部分以增加接合部分的接合面积，并且允许接合部件不仅接触接合部分的金属层，而且接触其电绝缘部分，从而改善接合 传感器和PCB之间的力。 结果，换能器可以可靠地结合到PCB，使得可以防止换能器的性能由于PCB和换能器之间的不良连接而劣化。

公开(公告)号：US08201133B2

公开(公告)日：2012-06-12

申请号：US12140730

申请日：2008-06-17

Applicant: Moises Cases ,  Tae H. Kim ,  Bhyrav M. Mutnury

Inventor： Moises Cases ,  Tae H. Kim ,  Bhyrav M. Mutnury

IPC: G06F17/50

CPC classification number: H05K1/0224 ,  H05K1/0225 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/0005 ,  H05K2201/09681 ,  Y10T29/49124

Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

Abstract translation: 具有降低的信号失真的印刷电路板，包括一层或多层不导电基底，在其上设置传导信号的导电路径，其特征在于至少部分地由印刷的层上的导电路径的取向引起的变形 电路板和周期性图案化参考平面; 每个导电通路相对于在印刷电路板上传导信号的其它导电通路传导正交或对角地定向四十五度的信号; 所述周期性图案化参考平面包括具有以周期性重复图案布置的不连续性的导体，所述不连续性的图案相对于在所述印刷电路板上传导信号的导电路径以最佳角度定向在所述印刷电路板的层的表面上 印刷电路板，可以减少信号的失真。

公开(公告)号：US20120138338A1

公开(公告)日：2012-06-07

申请号：US13365755

申请日：2012-02-03

Applicant: Han KIM ,  Hyung-Sik Choi ,  Dae-Hyun Park

Inventor： Han KIM ,  Hyung-Sik Choi ,  Dae-Hyun Park

IPC: H05K1/00

CPC classification number: H05K1/0236 ,  H05K1/0237 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09736 ,  H05K2201/09745

Abstract: A printed circuit board having stepped conduction layer includes at least one conduction layer configured for use as a signal transmission layer, the at least one conduction layer being divided into at least two base regions and at least one connecting region connecting any adjacent two of the base regions, and the connecting region being stepped to a lower height than those of the base regions. A lower surface of the connecting region lies on a same plane as a lower surface of the base region, or an upper surface of the connecting region lies on a same plane as an upper surface of the base region. A bridge connecting structure between the connecting regions and the base regions is disposed in possible noise transfer paths between a noise source and a noise attenuation target positioned on the printed circuit board.

Abstract translation: 具有阶梯式导电层的印刷电路板包括被配置为用作信号传输层的至少一个导电层，所述至少一个导电层被分成至少两个基极区域和至少一个连接区域， 区域，并且连接区域被阶梯到比基部区域低的高度。 连接区域的下表面位于与基底区域的下表面相同的平面上，或者连接区域的上表面位于与基底区域的上表面相同的平面上。 在连接区域和基极区域之间的桥连接结构设置在位于印刷电路板上的噪声源和噪声衰减目标之间的可能的噪声传递路径中。

公开(公告)号：US08169790B2

公开(公告)日：2012-05-01

申请号：US12010561

申请日：2008-01-25

Applicant: Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

Inventor： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC: H05K7/00

CPC classification number: H01P1/2005 ,  H01L2224/16225 ,  H01Q15/006 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/09681

Abstract: An electromagnetic bandgap structure and a printed circuit board having the electromagnetic bandgap that intercepts the transfer of a signal ranging a frequency band are disclosed. The electromagnetic bandgap structure includes a metal layer; a dielectric layer, stacked on the metal layer; at least two metal plates, stacked on the same planar surface of the dielectric layer; and a stitching via, connecting the adjacent metal plates. The stitching via passes through the dielectric layer, and a part of the stitching via is placed on the same planar surface of the metal layer. With the present invention, the electromagnetic bandgap can decrease the noise of a particular frequency by having a compact size and a low bandgap frequency.

Abstract translation: 公开了一种具有电磁带隙的电磁带隙结构和印刷电路板，该电磁带隙拦截了频带范围内的信号的传送。 电磁带隙结构包括金属层; 介电层，堆叠在金属层上; 至少两个金属板，堆叠在介电层的相同平面上; 和缝合通孔，连接相邻的金属板。 缝合通孔穿过电介质层，并且缝合通孔的一部分被放置在金属层的同一平面上。 利用本发明，电磁带隙可以通过具有紧凑的尺寸和低的带隙频率来降低​​特定频率的噪声。

公开(公告)号：US08077000B2

公开(公告)日：2011-12-13

申请号：US12232463

申请日：2008-09-17

Applicant: Ja-Bu Koo ,  Mi-Ja Han ,  Han Kim

Inventor： Ja-Bu Koo ,  Mi-Ja Han ,  Han Kim

IPC: H01P1/201

CPC classification number: H01P3/088 ,  H01L2224/16225 ,  H01P1/2005 ,  H05K1/0236 ,  H05K1/0237 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681

Abstract: Disclosed are an electromagnetic bandgap structure and a printed circuit board. In accordance with an embodiment of the present invention, the electromagnetic bandgap structure can include a dielectric layer; a plurality of conductive plates; a stitching via, configured to pass through the dielectric layer and have a part electrically connecting the conductive plates to each other by connecting through a planar surface that is different from a planar surface of the conductive plates, and a through via. Here, the dielectric layer, the conductive plates and the stitching via can be placed between any two conductive layers, and the through via can be configured to pass through a clearance hole formed in the conductive layer and electrically connect the two conductive layers to each other.

Abstract translation: 公开了电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构可以包括电介质层; 多个导电板; 缝合通孔，其构造成穿过介电层并且具有通过连接通过不同于导电板的平坦表面的平坦表面和通孔而将导电板彼此电连接的部分。 这里，电介质层，导电板和缝合通孔可以放置在任何两个导电层之间，并且通孔可以被配置为穿过形成在导电层中的间隙孔并将两个导电层彼此电连接 。