公开(公告)号：US07492146B2

公开(公告)日：2009-02-17

申请号：US11266892

申请日：2005-11-03

Applicant: Arash Behziz

Inventor： Arash Behziz

IPC: G01R31/28

CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/116 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: In one embodiment, a via structure for a printed circuit board is provided which includes a signal via and an elongated signal conductor strip electrically connected to the signal via. The elongated signal conductor strip is adjacent to a ground conductor and extends from the conductive pad substantially to the ground conductor. The elongated signal conductor strip includes a portion extending laterally outward, which may be configured to have a capacitance so as to establish an impedance for the via structure.

Abstract translation: 在一个实施例中，提供了一种用于印刷电路板的通孔结构，其包括电连接到信号通孔的信号通孔和细长的信号导体条。 细长的信号导体条与接地导体相邻并且从导电焊盘基本上延伸到接地导体。 细长信号导体条包括横向向外延伸的部分，其可以被配置为具有电容以便为通孔结构建立阻抗。

公开(公告)号：US07476965B2

公开(公告)日：2009-01-13

申请号：US11575751

申请日：2005-09-07

Applicant: Christian Val ,  Olivier Lignier ,  Regis Bocage

Inventor： Christian Val ,  Olivier Lignier ,  Regis Bocage

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0201 ,  H05K1/111 ,  H05K1/112 ,  H05K3/4641 ,  H05K2201/09718 ,  H05K2201/09745 ,  H05K2201/09781 ,  H05K2203/165 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract translation: 本发明涉及一种并入热分配器的电子设备。 它更具体地应用于塑料封装类型的器件，具有一个或多个级别的部件。 根据本发明，提供了例如封装类型的电子设备，用于其与分布在连接表面上的焊盘的外部连接。 它包括平行于所述连接表面并且具有不均匀结构的导热板，使得当设备暴露于给定的外部温度时，可以根据其在位置上的位置向每个外部连接垫提供受控量的热量 连接面。 如果设备是包括印刷电路类型的支撑体的封装，导电板将有利地形成所述支撑件的内层。

公开(公告)号：US07436681B2

公开(公告)日：2008-10-14

申请号：US11970163

申请日：2008-01-07

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area. The wiring board further includes: a line that electrically connects either one of a power pad for supplying power to the IC chip and a ground pad for grounding the IC chip to either one of the first lower electrode and the second lower electrode; and a line that electrically connects the other of the power pad and the ground pad to the other of the first upper electrode and the second upper electrode.

Abstract translation: 本发明提供一种具有内置电容器的布线板，其具有多层布线结构并且能够在其上安装IC芯片。 具有内置电容器的布线板包括：第一电容器，其内置在多层布线结构中，并且形成为使得设置在第一介电层的各个表面上的第一下电极和第一上电极之间的重叠区域是预定的 区; 以及第二电容器，其沿着与第一电介质层相同的平面内置在多层布线结构中，并且形成为使得第二下电极和第二上电极之间的重叠区域设置在具有该第二电介质层的第二电介质层的各个表面上 第一电介质层的厚度与预定面积不同。 所述布线基板还包括：将与所述IC芯片供电的功率垫中的任一个电连接的接线板和将所述IC芯片接地到所述第一下部电极和所述第二下部电极中的任一个的接地焊盘; 以及将所述电源焊盘和所述接地焊盘中的另一个电连接到所述第一上电极和所述第二上电极中的另一个的线。

公开(公告)号：US07422484B2

公开(公告)日：2008-09-09

申请号：US11522530

申请日：2006-09-18

Applicant: Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

Inventor： Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

IPC: H01R13/648

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

公开(公告)号：US20080075070A1

公开(公告)日：2008-03-27

申请号：US11978810

申请日：2007-10-30

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H04L12/50

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises signaling through-holes that pass through a plurality of layers, including signal trace and digital ground plane layers, and power reference plane layers. Clearances are set to achieve a desired impedance characteristic for the through-holes. At a power reference plane layer, the clearance is defined around multiple neighboring through-holes.

Abstract translation: 电路板包括通过多个层的信令通孔，包括信号迹线和数字接地层以及功率参考平面层。 设定间隙以实现通孔所需的阻抗特性。 在功率参考平面层上，间隙围绕多个相邻的通孔限定。

公开(公告)号：US20080023221A1

公开(公告)日：2008-01-31

申请号：US11565651

申请日：2006-12-01

Applicant: SHOU-KUO HSU ,  YU-CHANG PAI ,  CHENG-HONG LIU

Inventor： SHOU-KUO HSU ,  YU-CHANG PAI ,  CHENG-HONG LIU

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/116 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: An exemplary printed circuit board includes at least a pair of differential vias defined therein, each of the differential vias has an annular ring formed on the PCB, a conductive hole defined in the PCB, and a clearance hole defined in at least one inner layer of the PCB. Each of the clearance holes of the differential vias is oval shaped thus providing a greater area for the clearance holes and needed clearance between vias without creating a superposition zone.

Abstract translation: 示例性印刷电路板包括限定在其中的至少一对差分通孔，每个差分通孔具有形成在PCB上的环形圈，限定在PCB中的导电孔，以及限定在至少一个内层中的间隙孔 PCB。 差动通孔的每个间隙孔都是椭圆形的，从而为间隙孔提供了更大的面积，并且在通道之间需要间隙而不产生叠加区域。

公开(公告)号：US20070297157A1

公开(公告)日：2007-12-27

申请号：US11474339

申请日：2006-06-26

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area. The wiring board further includes: a line that electrically connects either one of a power pad for supplying power to the IC chip and a ground pad for grounding the IC chip to either one of the first lower electrode and the second lower electrode; and a line that electrically connects the other of the power pad and the ground pad to the other of the first upper electrode and the second upper electrode.

Abstract translation: 本发明提供一种具有内置电容器的布线板，其具有多层布线结构并且能够在其上安装IC芯片。 具有内置电容器的布线板包括：第一电容器，其内置在多层布线结构中，并且形成为使得设置在第一介电层的各个表面上的第一下电极和第一上电极之间的重叠区域是预定的 区; 以及第二电容器，其沿着与第一电介质层相同的平面内置在多层布线结构中，并且形成为使得第二下电极和第二上电极之间的重叠区域设置在具有该第二电介质层的第二电介质层的各个表面上 第一电介质层的厚度与预定面积不同。 所述布线基板还包括：将与所述IC芯片供电的功率垫中的任一个电连接的接线板和将所述IC芯片接地到所述第一下部电极和所述第二下部电极中的任一个的接地焊盘; 以及将所述电源焊盘和所述接地焊盘中的另一个电连接到所述第一上电极和所述第二上电极中的另一个的线。

公开(公告)号：US20070294890A1

公开(公告)日：2007-12-27

申请号：US11770581

申请日：2007-06-28

Applicant: Franz Gisin ,  Greg Schroeder

Inventor： Franz Gisin ,  Greg Schroeder

IPC: H01K3/10 ,  H03H7/38

CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09718 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A printed circuit board with improved signal integrity for one or more differential signal pairs incorporates one or more conductive regions. In an exemplary embodiment, via structures for the differential pair that interconnect signal traces are isolated from the conductive region by an antipad area around the via structures and a conductive bridge. In alternate embodiment, an antipad area around the via structures includes a bridge between the via structures. The antipad area may comprise, by way of non-limiting example, a clipped circular aperture or a modified rectangular aperture. The bridge may, by non-limiting examples, comprise a portion of the conductive region to permit impedance tailoring of the differential pair with respect to the conductive region.

Abstract translation: 对于一个或多个差分信号对具有改进的信号完整性的印刷电路板包括一个或多个导电区域。 在示例性实施例中，将信号迹线互连的差分对的通孔结构通过通孔结构和导电桥周围的反面区域与导电区域隔离。 在替代实施例中，通孔结构周围的止血区域包括通孔结构之间的桥。 作为非限制性示例，止血区域可以包括夹紧的圆形孔或修改的矩形孔。 通过非限制性示例，桥可以包括导电区域的一部分，以允许差分对相对于导电区域的阻抗调整。

公开(公告)号：US20070278001A1

公开(公告)日：2007-12-06

申请号：US11444943

申请日：2006-05-31

Applicant: Romi Mayder ,  Youhan Younan

Inventor： Romi Mayder ,  Youhan Younan

IPC: H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09718

Abstract: A high frequency coaxial through hole via in a multilayer printed circuit board is presented. The high frequency coaxial through hole via may include two traces connected by a plated through hole via and surrounded by more than one ground plane, where the more than one ground planes are capacitively coupled.

Abstract translation: 提出了一种多层印刷电路板中的高频同轴通孔通孔。 高频同轴通孔通孔可以包括由电镀通孔连接并由多于一个接地平面围绕的两个迹线，其中多于一个的接地层电容耦合。

公开(公告)号：US20070205847A1

公开(公告)日：2007-09-06

申请号：US10598134

申请日：2005-03-09

Applicant: Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

Inventor： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

IPC: H01P5/02

CPC classification number: H05K1/0222 ,  H05K1/0269 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predetermined clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.

Abstract translation: 一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件， 多层PCB的导体层的接地板组以及间隙孔。 在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部 通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置 根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。