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    Electronic circuit
    64.
    发明授权
    Electronic circuit 有权
    电子电路

    公开(公告)号：US08350259B2

    公开(公告)日：2013-01-08

    申请号：US12994170

    申请日：2009-05-29

    Applicant: Alexander Knobloch ,  Walter Fix

    Inventor： Alexander Knobloch ,  Walter Fix

    IPC: H01L29/08 ,  H01L29/66 ,  H01J63/04

    CPC classification number: H01L27/283 ,  H01L51/0018 ,  H05K1/0393 ,  H05K1/16 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/09763 ,  H05K2201/09909

    Abstract: An electronic circuit includes at least two organic components interconnected by conductor tracks and having a common carrier substrate. The components and the conductor tracks are formed from layer portions. An uppermost layer portion, remote from the carrier substrate, of the electronic circuit is of a patterned configuration comprising an electrically conducting material. The patterned uppermost layer portion on its side remote from the carrier substrate is provided with at least one protective layer arranged in congruent relationship with the uppermost layer portion. The at least two organic components include at least one first component of a first component type and at least one second component of a second component type different therefrom. Components of the same component type are respectively protected by a protective layer of the same composition and/or the same structure corresponding to that component type and differing from one another according to the corresponding component type.

    Abstract translation: 电子电路包括至少两个由导体轨道互连并具有公共载体衬底的有机部件。 部件和导体轨道由层部分形成。 远离电子电路的载体衬底的最上层部分是包括导电材料的图案化构造。 远离载体基板的图案化的最上层部分设置有与最上层部分一致布置的至少一个保护层。 所述至少两种有机组分包括至少一种第一组分类型的第一组分和与其不同的第二组分类型的至少一种第二组分。 相同组件类型的组件分别由与该组件类型对应的相同组成和/或相同结构的保护层保护，并且根据相应的组件类型彼此不同。

    MULTILAYER PRINTED WIRING BOARD
    65.
    发明申请
    MULTILAYER PRINTED WIRING BOARD 有权
    多层印刷接线板

    公开(公告)号：US20120302010A1

    公开(公告)日：2012-11-29

    申请号：US13561247

    申请日：2012-07-30

    Applicant: Takashi KARIYA ,  Akira Mochida

    Inventor： Takashi KARIYA ,  Akira Mochida

    IPC: H01L21/58

    CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

    Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

    Abstract translation: 一种制造印刷电路板的方法包括在第一金属层上形成含有原料陶瓷材料的未煅烧层，焙烧形成在第一金属层上的未煅烧层，使得具有以片状形式煅烧的陶瓷体的高介电常数层 形成在第一金属层上，相对于第一金属层在高介电常数层的相对侧的高介电常数层上形成第二金属层，使得具有高介电常数层的层状电容器和第一金属层 形成夹着高介电常数层的第二层电极，并将层叠电容器配置在主体中。

    Electronic component and electronic component module
    66.
    发明授权
    Electronic component and electronic component module 有权
    电子元件和电子元件模块

    公开(公告)号：US08294036B2

    公开(公告)日：2012-10-23

    申请号：US12410699

    申请日：2009-03-25

    Applicant: Shinichiro Kakei ,  Kenji Horino ,  Hitoshi Saita ,  Yasunobu Oikawa

    Inventor： Shinichiro Kakei ,  Kenji Horino ,  Hitoshi Saita ,  Yasunobu Oikawa

    IPC: H05K1/16 ,  H05K1/18

    CPC classification number: H05K1/162 ,  H05K3/382 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/033

    Abstract: In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.

    Abstract translation: 在电介质元件中，侧面粗糙化，使得表面粗糙度Ra为15nm以上。 通过这种方式，玻璃环氧树脂基板和绝缘材料之间的接触面积增加，与树脂基板的粘合性提高，并且当埋在两个树脂基板之间时可以提高强度和可靠性。 在电介质元件中，侧面的表面粗糙度Ra为5000nm以下，因此当在玻璃环氧树脂基板和绝缘材料之间埋入电介质元件时，介电元件表面与树脂之间产生气泡 可以防止。

    Method for fabricating circuit board structure with capacitors embedded therein
    68.
    发明授权
    Method for fabricating circuit board structure with capacitors embedded therein 有权
    制造电容器结构的方法，其中嵌入电容器

    公开(公告)号：US08256106B2

    公开(公告)日：2012-09-04

    申请号：US12010345

    申请日：2008-01-24

    Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

    Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

    IPC: H05K1/16 ,  H05K3/02 ,  H05K3/32 ,  H05K3/42 ,  H05K3/46

    CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

    Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

    Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法。 该结构包括至少两个核心层，其单独地包括具有两个相对表面的电介质层，设置在电介质层的两个相对表面的外侧的电路层，以及分别嵌入在介电层的两个相对表面的内部的内部的至少两个电容器 所述电介质层与所述电路层在同一侧分别电连接; 设置在所述芯层之间的至少一个粘合剂层，以将所述芯层组合为芯结构; 以及穿透芯层和粘合剂层的至少一个导电通孔，并且电连接芯层的电路层。 因此，本发明可以提高电路布局的灵活性，并且实现电容器之间的并联以提供更多的电容。

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