公开(公告)号：US20100116540A1

公开(公告)日：2010-05-13

申请号：US12611261

申请日：2009-11-03

Applicant: Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

Inventor： Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

IPC: H05K1/11 ,  B05D5/12

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/06 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: An end of a first line and an end of a second line of a first write wiring pattern are arranged on both sides of a third line of a second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. In addition, through holes are formed in respective portions of a base insulating layer below the connection portions. Each connection portion comes in contact with a connecting region of a suspension body within the through hole.

Abstract translation: 第一写入布线图案的第一行的一端和第二行的末端布置在第二写入布线图案的第三行的两侧。 圆形连接部设置在第一线和第二线的端部。 此外，在连接部分下方的基底绝缘层的各个部分中形成通孔。 每个连接部分与通孔内的悬架体的连接区域接触。

公开(公告)号：US20100032200A1

公开(公告)日：2010-02-11

申请号：US12581205

申请日：2009-10-19

Applicant: Naohiro HIROSE ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

Inventor： Naohiro HIROSE ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

IPC: H05K1/11

CPC classification number: H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract translation: 一种包含衬底的封装衬底310，该衬底设置有导体层5，导电连接销100被布置成与主板建立电连接并固定到衬底的表面，其中提供用于固定导电连接销的焊盘16，用于 封装衬底310.衬垫16被具有开口18的有机树脂绝缘层15覆盖，衬垫16通过该开口局部暴露于外部。 导电连接销100通过导电粘合剂17通过开口固定到暴露于外部的焊盘，从而防止例如当执行安装时发生例如导电连接销100从基板的溶液。

公开(公告)号：US20100032196A1

公开(公告)日：2010-02-11

申请号：US12537391

申请日：2009-08-07

Applicant: Kentaro KANEKO ,  Kazuhiro Kobayashi ,  Yoshiki Okushima ,  Kotaro Kodani

Inventor： Kentaro KANEKO ,  Kazuhiro Kobayashi ,  Yoshiki Okushima ,  Kotaro Kodani

IPC: H05K1/16 ,  H05K1/11 ,  B32B37/00

CPC classification number: H05K1/113 ,  B32B37/02 ,  B32B2457/08 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/02 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/20 ,  H05K3/421 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/037 ,  H05K2201/09527 ,  H05K2201/0979 ,  H05K2201/09981 ,  Y10T156/10 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a multilayer wiring board having a wiring layer, a pad, an insulating layer provided between the wiring layer and the pad, and a plurality of connecting vias provided on the insulating layer and connecting the wiring layer to the pad, the connecting vias are provided on a peripheral edge of the pad.

Abstract translation: 在具有布线层，焊盘，设置在布线层和焊盘之间的绝缘层以及设置在绝缘层上并将布线层连接到焊盘的多个连接通孔的多层布线板中，提供连接通孔 在垫的外围边缘。

公开(公告)号：US07651382B2

公开(公告)日：2010-01-26

申请号：US12127195

申请日：2008-05-27

Applicant: Gary Yasumura ,  Joseph C. Fjelstad ,  Kevin P. Grundy ,  William F. Wiedemann ,  Matthew J. Stepovich

Inventor： Gary Yasumura ,  Joseph C. Fjelstad ,  Kevin P. Grundy ,  William F. Wiedemann ,  Matthew J. Stepovich

IPC: H01R4/48

CPC classification number: H01R13/2407 ,  H01R12/714 ,  H01R12/79 ,  H01R13/658 ,  H05K3/326 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/0979

Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.

Abstract translation: 一种电互连装置，用于在要配合的两个导电元件的端部之间建立冗余触点，产生不具有电容短截线的电互连。

公开(公告)号：US07638419B2

公开(公告)日：2009-12-29

申请号：US11948748

申请日：2007-11-30

Applicant: Erik W. Jensen

Inventor： Erik W. Jensen

IPC: H01L21/44 ,  H05K3/00 ,  H01L23/48 ,  H05K1/11 ,  H05K7/10

CPC classification number: H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09381 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: Various embodiments include a method of forming an interconnect comprising forming at least two vias in a substrate, forming a conductive pad on a surface of the substrate, forming at least one tapered conductive segment on the surface of the substrate coupled to the conductive pad, wherein only a first via of the at least two vias is formed substantially beneath the conductive pad and is coupled to the conductive pad, a second via of the at least two vias is coupled to the conductive pad by a first one of the at least one tapered conductive segments, the first one of the tapered conductive segments having a first end having a first width and a second end having a second width, the first end being connected to the second via and the second end being connected to the conductive pad, the first width being less than the second width.

Abstract translation: 各种实施例包括形成互连的方法，包括在衬底中形成至少两个通孔，在衬底的表面上形成导电焊盘，在耦合到导电焊盘的衬底的表面上形成至少一个锥形导电段，其中 只有至少两个通孔的第一通孔形成在导电焊盘的基本下方，并且耦合到导电焊盘，所述至少两个通孔的第二通孔通过所述至少一个锥形 导电段，第一个锥形导电段具有第一端和第二端，第一端具有第一宽度，第二端具有第二宽度，第一端连接到第二通孔，第二端连接到导电垫， 宽度小于第二宽度。

公开(公告)号：US20090315855A1

公开(公告)日：2009-12-24

申请号：US12485615

申请日：2009-06-16

Applicant: Harutoshi OIKAWA ,  Kiyohiro KIMURA

Inventor： Harutoshi OIKAWA ,  Kiyohiro KIMURA

IPC: G06F3/045 ,  H05K1/02

CPC classification number: H05K3/361 ,  H05K3/281 ,  H05K3/323 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2203/1572

Abstract: A flexible printed circuit includes: a flexible substrate extending from a first end section to a second end section, and having an opening or a notch in proximity to the first end section; a first wiring layer extending from the first end section to the second end section so as to avoid the opening or the notch; a second wiring layer extending from the first end section to the second end section so as to block the opening or the notch; a first conductive member being formed opposed to the flexible substrate in relation to the first wiring layer and at least in proximity to the first end section in a region opposed to the first wiring layer, and being electrically connected to the first wiring layer; and a second conductive member electrically connected to the second wiring layer via the opening or the notch.

Abstract translation: 柔性印刷电路包括：柔性基板，其从第一端部延伸到第二端部，并且具有靠近第一端部的开口或凹口; 第一布线层，从第一端部延伸到第二端部，以避免开口或凹口; 第二布线层，其从所述第一端部延伸到所述第二端部，以阻挡所述开口或所述凹口; 第一导电构件，其与所述柔性基板相对于所述第一布线层形成，并且在与所述第一布线层相对的区域中至少靠近所述第一端部，并且电连接到所述第一布线层; 以及通过所述开口或所述凹口与所述第二布线层电连接的第二导电构件。

公开(公告)号：US07630208B2

公开(公告)日：2009-12-08

申请号：US12198342

申请日：2008-08-26

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H05K1/16

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01G4/385 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/09309 ,  H05K2201/09772 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Abstract translation: 本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。 第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极， 并且第一至第四内部电极耦合到第一至第四外部电极。 第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。

公开(公告)号：US07615706B2

公开(公告)日：2009-11-10

申请号：US11508057

申请日：2006-08-21

Applicant: Cheng-Hsin Chen ,  Kuang-Cheng Kao ,  Chen-Yu Yang

Inventor： Cheng-Hsin Chen ,  Kuang-Cheng Kao ,  Chen-Yu Yang

IPC: H05K1/16

CPC classification number: G02F1/13452 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/244 ,  H05K3/361 ,  H05K2201/0326 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A layout of a printed circuit board adaptive to be bonded to an integrated circuit device is introduced here. The layout includes a first metal layer, disposed in a first insulation layer and a second metal layer, disposed in a second insulation layer over the first insulation layer. The first metal layer and the second metal layer are connected to each other through a plurality of contact hole filled with conductive materials and are arranged to be substantially parallel to each other throughout a pad structure region and a line structure region of the printed circuit. The connected first metal layer and second metal layer are used for a signal path from the printed circuit board to the bonded integrated circuit device to improve driving ability of power supply.

Abstract translation: 这里介绍了适合于结合到集成电路器件的印刷电路板的布局。 布置包括设置在第一绝缘层和第二金属层上的第一金属层，设置在第一绝缘层上的第二绝缘层中。 第一金属层和第二金属层通过填充有导电材料的多个接触孔彼此连接，并且布置成在整个衬垫结构区域和印刷电路的线结构区域中彼此大致平行。 连接的第一金属层和第二金属层用于从印刷电路板到结合集成电路器件的信号路径，以提高电源的驱动能力。

公开(公告)号：US07532479B2

公开(公告)日：2009-05-12

申请号：US11707884

申请日：2007-02-20

Applicant: Yasuo Ohno ,  Chiharu Ota

Inventor： Yasuo Ohno ,  Chiharu Ota

IPC: H05K7/20

CPC classification number: H05K1/112 ,  G02B6/0073 ,  G02B6/0083 ,  G02B6/0085 ,  H01L33/64 ,  H01L33/641 ,  H05K1/0206 ,  H05K3/0061 ,  H05K3/305 ,  H05K3/3442 ,  H05K2201/0209 ,  H05K2201/09072 ,  H05K2201/0979 ,  H05K2201/10106 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: In a spread illuminating apparatus including: an LED at a side surface of a light conductor plate; and an FPC having a land formed on a side thereof for mounting the LED, throughholes are formed at the land, and solder is contained at least partly in each of the throughholes, whereby the LED can be mounted solidly on the FPC with a high precision in height position from the FPC, and at the same time the heat emitted from the LED can be efficiently conducted to a conductive pattern at the rear side of the FPC through an electrode terminal of the LED and the throughholes filled with the solder composed of a metallic material having a high heat conductance.

Abstract translation: 一种扩展照明装置，包括：在导光板的侧面的LED; 并且具有形成在其一侧的用于安装LED的边缘的FPC，在该焊盘处形成通孔，并且焊料至少部分地包含在每个通孔中，由此可以以高精度将LED牢固地安装在FPC上 从FPC的高度位置，并且同时从LED发射的热可以通过LED的电极端子和填充有由焊料组成的焊料的通孔有效地传导到FPC背面的导电图案 具有高导热性的金属材料。

公开(公告)号：US20090095519A1

公开(公告)日：2009-04-16

申请号：US11872870

申请日：2007-10-16

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H05K1/00 ,  H05K3/42

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种电气结构和成型方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。