公开(公告)号：US12142566B2

公开(公告)日：2024-11-12

申请号：US18206539

申请日：2023-06-06

Applicant: Intel Corporation

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20240290788A1

公开(公告)日：2024-08-29

申请号：US18175591

申请日：2023-02-28

Applicant: Intel Corporation

Inventor： Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Robin Chao ,  David Towner ,  Orb Acton ,  Omair Saadat ,  Feng Zhang ,  Dax M. Crum ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

公开(公告)号：US11908856B2

公开(公告)日：2024-02-20

申请号：US16719257

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US11621395B2

公开(公告)日：2023-04-04

申请号：US16396465

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

公开(公告)号：US11616192B2

公开(公告)日：2023-03-28

申请号：US16024599

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tofizur Rahman ,  Christopher J. Wiegand ,  Justin S. Brockman ,  Daniel G. Ouellette ,  Angeline K. Smith ,  Andrew Smith ,  Pedro A. Quintero ,  Juan G. Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.

公开(公告)号：US11489112B2

公开(公告)日：2022-11-01

申请号：US16641582

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Namrata S. Asuri ,  Oleg Golonzka ,  Nathan Strutt ,  Patrick J. Hentges ,  Trinh T. Van ,  Hiten Kothari ,  Ameya S. Chaudhari ,  Matthew J. Andrus ,  Timothy E. Glassman ,  Dragos Seghete ,  Christopher J. Wiegand ,  Daniel G. Ouellette

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

公开(公告)号：US11430948B2

公开(公告)日：2022-08-30

申请号：US16641588

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Timothy Glassman ,  Dragos Seghete ,  Nathan Strutt ,  Namrata S. Asuri ,  Oleg Golonzka ,  Hiten Kothari ,  Matthew J. Andrus

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

公开(公告)号：US11430944B2

公开(公告)日：2022-08-30

申请号：US16358671

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Christopher Wiegand ,  Gokul Malyavanatham ,  Oleg Golonzka

IPC: H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  H01L43/12

Abstract: An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.

公开(公告)号：US10943950B2

公开(公告)日：2021-03-09

申请号：US16367126

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Daniel Ouellette ,  Christopher Wiegand ,  Justin Brockman ,  Tofizur Rahman ,  Oleg Golonzka ,  Angeline Smith ,  Andrew Smith ,  James Pellegren ,  Aaron Littlejohn ,  Michael Robinson ,  Huiying Liu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.

公开(公告)号：US10910265B2

公开(公告)日：2021-02-02

申请号：US16801113

申请日：2020-02-25

Applicant: Intel Corporation

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/306 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/66 ,  H01L21/28 ,  H01L23/535 ,  H01L29/06 ,  H01L21/32

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.